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@pavelkryukov pavelkryukov released this 07 May 21:03
b39ebe4

98% test coverage!

RISC-V

System simulation

Branch prediction

Cache improvements by Andrey Agrachev

  • Infrastructure for cache replacement policies
  • Pseudo-LRU replacement policy
  • Use of Google Dense Hash for simulation speed

Execution pipeline improvement by Egor Bova

  • Initial support for multi-wide writeback stage

MIPS

  • Generation of MIPS traps by Vsevolod Pukhov
  • Unit tests for MIPS instructions by Egor Bova. Bug fixes:
    • Treat dadd and daddu as MIPS III instructions
    • Fix of 64-bit multiplication on x86 targets and/or VS builds
    • Branch-and-link instructions should link even if not taken
    • Use only LSB of the variable shift RHS operand (#709)
  • Decoding of CP1 (floating point) instructions by Egor Bova.
  • Support of branch delay slot by Pavel Kryukov and Andrey Agrachev
  • Big-endian MIPS by Pavel Kryukov

Complete refactoring of port system by Pavel Kryukov

  • Dynamic type matching
  • Self-cleaning
  • Arena allocations with optimizations for POD-based data structures
  • Type erasure for ports to reduce amount of templates
  • Translation of port templates in a separate translation unit
  • As a result, 1.5x simulation speed and 2x compilation speed boosts

New manuals

External PRs: