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Move port consts to inner scope
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@pavelkryukov
pavelkryukov committed Apr 26, 2020
1 parent c6385cc commit 30b31f0
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Showing 11 changed files with 117 additions and 119 deletions.
10 changes: 5 additions & 5 deletions simulator/infra/ports/ports.h
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Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,11 @@ class Port : public Log
public:
const std::string& get_key() const noexcept { return k; }

static constexpr const Latency LATENCY = 1_lt;
static constexpr const Latency LONG_LATENCY = 30_lt;
static constexpr const uint32 FANOUT = 1;
static constexpr const uint32 BW = 1;

protected:
Port( std::shared_ptr<PortMap> port_map, std::string key);
std::shared_ptr<PortMap> get_port_map() const noexcept { return pm; }
Expand Down Expand Up @@ -235,9 +240,4 @@ void WritePort<T>::add_reader( BasicReadPort* reader)
destinations.emplace_back( r);
}

static inline constexpr const Latency PORT_LATENCY = 1_lt;
static inline constexpr const Latency PORT_LONG_LATENCY = 30_lt;
static inline constexpr const uint32 PORT_FANOUT = 1;
static inline constexpr const uint32 PORT_BW = 1;

#endif // PORTS_H
16 changes: 8 additions & 8 deletions simulator/infra/ports/t/example_test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -43,10 +43,10 @@ class A : public Module
public:
explicit A( Module* root) : Module( root, "A")
{
to_B = make_write_port<int>( "A_to_B", PORT_BW);
from_B = make_read_port<int>( "B_to_A", PORT_LATENCY);
init = make_read_port<int>( "init_A", PORT_LATENCY);
stop = make_write_port<bool>( "stop", PORT_BW);
to_B = make_write_port<int>( "A_to_B", Port::BW);
from_B = make_read_port<int>( "B_to_A", Port::LATENCY);
init = make_read_port<int>( "init_A", Port::LATENCY);
stop = make_write_port<bool>( "stop", Port::BW);
}

void clock( Cycle cycle)
Expand Down Expand Up @@ -88,8 +88,8 @@ class B : public Module
public:
explicit B( Module* root) : Module( root, "B")
{
to_A = make_write_port<int>( "B_to_A", PORT_BW);
from_A = make_read_port<int>( "A_to_B", PORT_LATENCY);
to_A = make_write_port<int>( "B_to_A", Port::BW);
from_A = make_read_port<int>( "A_to_B", Port::LATENCY);
};

void clock( Cycle cycle)
Expand All @@ -114,8 +114,8 @@ class TestRoot : public Root
public:
TestRoot() : Root( "test-root"), a( this), b( this)
{
init = make_write_port<int>( "init_A", PORT_BW);
stop = make_read_port<bool>( "stop", PORT_LATENCY);
init = make_write_port<int>( "init_A", Port::BW);
stop = make_read_port<bool>( "stop", Port::LATENCY);
init_portmap();
CHECK( init->get_fanout() == 1);

Expand Down
32 changes: 16 additions & 16 deletions simulator/infra/ports/t/topology_test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -32,10 +32,10 @@ struct SomeTopology : public Root
ReadPort<int>* from_D;
explicit A( Module* root) : TestModule( root, "A")
{
to_C = make_write_port<int>( "A_to_C", PORT_BW);
to_D = make_write_port<int>( "A_to_D", PORT_BW);
from_C = make_read_port<int>( "C_to_A", PORT_LATENCY);
from_D = make_read_port<int>( "D_to_A", PORT_LATENCY);
to_C = make_write_port<int>( "A_to_C", Port::BW);
to_D = make_write_port<int>( "A_to_D", Port::BW);
from_C = make_read_port<int>( "C_to_A", Port::LATENCY);
from_D = make_read_port<int>( "D_to_A", Port::LATENCY);
}
};
struct B : public TestModule {
Expand All @@ -45,10 +45,10 @@ struct SomeTopology : public Root
ReadPort<int>* from_D;
explicit B( Module* root) : TestModule( root, "B")
{
to_C = make_write_port<int>( "B_to_C", PORT_BW);
to_D = make_write_port<int>( "B_to_D", PORT_BW);
from_C = make_read_port<int>( "C_to_B", PORT_LATENCY);
from_D = make_read_port<int>( "D_to_B", PORT_LATENCY);
to_C = make_write_port<int>( "B_to_C", Port::BW);
to_D = make_write_port<int>( "B_to_D", Port::BW);
from_C = make_read_port<int>( "C_to_B", Port::LATENCY);
from_D = make_read_port<int>( "D_to_B", Port::LATENCY);
}
};
struct C : public TestModule {
Expand All @@ -58,10 +58,10 @@ struct SomeTopology : public Root
ReadPort<int>* from_B;
explicit C( Module* root) : TestModule( root, "C")
{
to_A = make_write_port<int>( "C_to_A", PORT_BW);
to_B = make_write_port<int>( "C_to_B", PORT_BW);
from_A = make_read_port<int>( "A_to_C", PORT_LATENCY);
from_B = make_read_port<int>( "B_to_C", PORT_LATENCY);
to_A = make_write_port<int>( "C_to_A", Port::BW);
to_B = make_write_port<int>( "C_to_B", Port::BW);
from_A = make_read_port<int>( "A_to_C", Port::LATENCY);
from_B = make_read_port<int>( "B_to_C", Port::LATENCY);
}
};
struct D : public TestModule {
Expand All @@ -71,10 +71,10 @@ struct SomeTopology : public Root
ReadPort<int>* from_B;
explicit D( Module* root) : TestModule( root, "D")
{
to_A = make_write_port<int>( "D_to_A", PORT_BW);
to_B = make_write_port<int>( "D_to_B", PORT_BW);
from_A = make_read_port<int>( "A_to_D", PORT_LATENCY);
from_B = make_read_port<int>( "B_to_D", PORT_LATENCY);
to_A = make_write_port<int>( "D_to_A", Port::BW);
to_B = make_write_port<int>( "D_to_B", Port::BW);
from_A = make_read_port<int>( "A_to_D", Port::LATENCY);
from_B = make_read_port<int>( "B_to_D", Port::LATENCY);
}
};
A a;
Expand Down
22 changes: 10 additions & 12 deletions simulator/infra/ports/t/unit_test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7,13 +7,11 @@
#include <catch.hpp>
#include <infra/ports/module.h>

static std::string port_latency_to_string = PORT_LATENCY.to_string();

TEST_CASE( "Latency to string")
{
CHECK( ( 5_cl).to_string() == "5");
CHECK( ( 2_lt).to_string() == "2");
CHECK( port_latency_to_string == "1");
CHECK( Port::LATENCY.to_string() == "1");
}

struct BaseTestRoot : public Root
Expand All @@ -27,7 +25,7 @@ TEST_CASE("Ports: no write port")
{
TestRoot()
{
make_read_port<int>( "Key", PORT_LATENCY);
make_read_port<int>( "Key", Port::LATENCY);
CHECK_THROWS_AS( init_portmap(), PortError);
}
} tr;
Expand All @@ -39,7 +37,7 @@ TEST_CASE("Ports: no read port")
{
TestRoot()
{
make_write_port<int>( "Yek", PORT_BW);
make_write_port<int>( "Yek", Port::BW);
CHECK_THROWS_AS( init_portmap(), PortError);
}
} tr;
Expand All @@ -51,9 +49,9 @@ TEST_CASE("Ports: two write ports")
{
TestRoot()
{
make_read_port<int>( "Key", PORT_LATENCY);
make_write_port<int>( "Key", PORT_BW);
CHECK_THROWS_AS( make_write_port<int>( "Key", PORT_BW), PortError);
make_read_port<int>( "Key", Port::LATENCY);
make_write_port<int>( "Key", Port::BW);
CHECK_THROWS_AS( make_write_port<int>( "Key", Port::BW), PortError);
}
} tr;
}
Expand All @@ -64,8 +62,8 @@ TEST_CASE("Ports: type mismatch")
{
TestRoot()
{
make_read_port<int>( "Key", PORT_LATENCY);
make_write_port<std::string>( "Key", PORT_BW);
make_read_port<int>( "Key", Port::LATENCY);
make_write_port<std::string>( "Key", Port::BW);
CHECK_THROWS_AS( init_portmap(), PortError);
}
} tr;
Expand All @@ -78,8 +76,8 @@ struct PairOfPorts : public BaseTestRoot

PairOfPorts()
{
rp = make_read_port<int>( "Key", PORT_LATENCY);
wp = make_write_port<int>( "Key", PORT_BW);
rp = make_read_port<int>( "Key", Port::LATENCY);
wp = make_write_port<int>( "Key", Port::BW);
init_portmap();
}
};
Expand Down
18 changes: 9 additions & 9 deletions simulator/modules/branch/branch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9,19 +9,19 @@
template <typename FuncInstr>
Branch<FuncInstr>::Branch( Module* parent) : Module( parent, "branch")
{
wp_flush_all = make_write_port<bool>("BRANCH_2_ALL_FLUSH", PORT_BW);
rp_flush = make_read_port<bool>("BRANCH_2_ALL_FLUSH", PORT_LATENCY);
rp_trap = make_read_port<bool>("WRITEBACK_2_ALL_FLUSH", PORT_LATENCY);
wp_flush_all = make_write_port<bool>("BRANCH_2_ALL_FLUSH", Port::BW);
rp_flush = make_read_port<bool>("BRANCH_2_ALL_FLUSH", Port::LATENCY);
rp_trap = make_read_port<bool>("WRITEBACK_2_ALL_FLUSH", Port::LATENCY);

wp_flush_target = make_write_port<Target>("BRANCH_2_FETCH_TARGET", PORT_BW);
wp_bp_update = make_write_port<BPInterface>("BRANCH_2_FETCH", PORT_BW);
wp_flush_target = make_write_port<Target>("BRANCH_2_FETCH_TARGET", Port::BW);
wp_bp_update = make_write_port<BPInterface>("BRANCH_2_FETCH", Port::BW);

rp_datapath = make_read_port<Instr>("EXECUTE_2_BRANCH", PORT_LATENCY);
wp_datapath = make_write_port<Instr>("BRANCH_2_WRITEBACK" , PORT_BW );
rp_datapath = make_read_port<Instr>("EXECUTE_2_BRANCH", Port::LATENCY);
wp_datapath = make_write_port<Instr>("BRANCH_2_WRITEBACK" , Port::BW );

wp_bypass = make_write_port<InstructionOutput>("BRANCH_2_EXECUTE_BYPASS", PORT_BW);
wp_bypass = make_write_port<InstructionOutput>("BRANCH_2_EXECUTE_BYPASS", Port::BW);

wp_bypassing_unit_flush_notify = make_write_port<bool>("BRANCH_2_BYPASSING_UNIT_FLUSH_NOTIFY", PORT_BW);
wp_bypassing_unit_flush_notify = make_write_port<bool>("BRANCH_2_BYPASSING_UNIT_FLUSH_NOTIFY", Port::BW);
}

template <typename FuncInstr>
Expand Down
4 changes: 2 additions & 2 deletions simulator/modules/core/perf_sim.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -21,13 +21,13 @@ PerfSim<ISA>::PerfSim( Endian endian, std::string_view isa)
, endian( endian)
, fetch( this), decode( this), execute( this), mem( this), branch( this), writeback( this, endian)
{
rp_halt = make_read_port<Trap>("WRITEBACK_2_CORE_HALT", PORT_LATENCY);
rp_halt = make_read_port<Trap>("WRITEBACK_2_CORE_HALT", Port::LATENCY);

decode.set_RF( &rf);
writeback.set_RF( &rf);
writeback.set_driver( ISA::create_driver( this));

set_writeback_bandwidth( PORT_BW);
set_writeback_bandwidth( Port::BW);

init_portmap();
enable_logging( config::units_to_log);
Expand Down
34 changes: 17 additions & 17 deletions simulator/modules/decode/decode.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16,23 +16,23 @@ Decode<FuncInstr>::Decode( Module* parent) : Module( parent, "decode")
{
bypassing_unit = std::make_unique<BypassingUnit>( config::long_alu_latency);

rp_datapath = make_read_port<Instr>("FETCH_2_DECODE", PORT_LATENCY);
rp_stall_datapath = make_read_port<Instr>("DECODE_2_DECODE", PORT_LATENCY);
rp_flush = make_read_port<bool>("BRANCH_2_ALL_FLUSH", PORT_LATENCY);
rp_bypassing_unit_notify = make_read_port<Instr>("DECODE_2_BYPASSING_UNIT_NOTIFY", PORT_LATENCY);
rp_bypassing_unit_flush_notify = make_read_port<bool>("BRANCH_2_BYPASSING_UNIT_FLUSH_NOTIFY", PORT_LATENCY);
rp_flush_fetch = make_read_port<bool>("DECODE_2_FETCH_FLUSH", PORT_LATENCY);
rp_trap = make_read_port<bool>("WRITEBACK_2_ALL_FLUSH", PORT_LATENCY);

wp_datapath = make_write_port<Instr>("DECODE_2_EXECUTE", PORT_BW);
wp_stall_datapath = make_write_port<Instr>("DECODE_2_DECODE", PORT_BW);
wp_stall = make_write_port<bool>("DECODE_2_FETCH_STALL", PORT_BW);
wps_command[0] = make_write_port<BypassCommand<Register>>("DECODE_2_EXECUTE_SRC1_COMMAND", PORT_BW);
wps_command[1] = make_write_port<BypassCommand<Register>>("DECODE_2_EXECUTE_SRC2_COMMAND", PORT_BW);
wp_bypassing_unit_notify = make_write_port<Instr>("DECODE_2_BYPASSING_UNIT_NOTIFY", PORT_BW);
wp_flush_fetch = make_write_port<bool>("DECODE_2_FETCH_FLUSH", PORT_BW);
wp_flush_target = make_write_port<Target>("DECODE_2_FETCH_TARGET", PORT_BW);
wp_bp_update = make_write_port<BPInterface>("DECODE_2_FETCH", PORT_BW);
rp_datapath = make_read_port<Instr>("FETCH_2_DECODE", Port::LATENCY);
rp_stall_datapath = make_read_port<Instr>("DECODE_2_DECODE", Port::LATENCY);
rp_flush = make_read_port<bool>("BRANCH_2_ALL_FLUSH", Port::LATENCY);
rp_bypassing_unit_notify = make_read_port<Instr>("DECODE_2_BYPASSING_UNIT_NOTIFY", Port::LATENCY);
rp_bypassing_unit_flush_notify = make_read_port<bool>("BRANCH_2_BYPASSING_UNIT_FLUSH_NOTIFY", Port::LATENCY);
rp_flush_fetch = make_read_port<bool>("DECODE_2_FETCH_FLUSH", Port::LATENCY);
rp_trap = make_read_port<bool>("WRITEBACK_2_ALL_FLUSH", Port::LATENCY);

wp_datapath = make_write_port<Instr>("DECODE_2_EXECUTE", Port::BW);
wp_stall_datapath = make_write_port<Instr>("DECODE_2_DECODE", Port::BW);
wp_stall = make_write_port<bool>("DECODE_2_FETCH_STALL", Port::BW);
wps_command[0] = make_write_port<BypassCommand<Register>>("DECODE_2_EXECUTE_SRC1_COMMAND", Port::BW);
wps_command[1] = make_write_port<BypassCommand<Register>>("DECODE_2_EXECUTE_SRC2_COMMAND", Port::BW);
wp_bypassing_unit_notify = make_write_port<Instr>("DECODE_2_BYPASSING_UNIT_NOTIFY", Port::BW);
wp_flush_fetch = make_write_port<bool>("DECODE_2_FETCH_FLUSH", Port::BW);
wp_flush_target = make_write_port<Target>("DECODE_2_FETCH_TARGET", Port::BW);
wp_bp_update = make_write_port<BPInterface>("DECODE_2_FETCH", Port::BW);
}

template <typename FuncInstr>
Expand Down
42 changes: 21 additions & 21 deletions simulator/modules/execute/execute.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16,37 +16,37 @@ template <typename FuncInstr>
Execute<FuncInstr>::Execute( Module* parent) : Module( parent, "execute")
, last_execution_stage_latency( Latency( config::long_alu_latency - 1))
{
wp_mem_datapath = make_write_port<Instr>("EXECUTE_2_MEMORY" , PORT_BW );
wp_branch_datapath = make_write_port<Instr>("EXECUTE_2_BRANCH" , PORT_BW );
wp_writeback_datapath = make_write_port<Instr>("EXECUTE_2_WRITEBACK", PORT_BW);
rp_datapath = make_read_port<Instr>("DECODE_2_EXECUTE", PORT_LATENCY);
rp_trap = make_read_port<bool>("WRITEBACK_2_ALL_FLUSH", PORT_LATENCY);
wp_mem_datapath = make_write_port<Instr>("EXECUTE_2_MEMORY" , Port::BW );
wp_branch_datapath = make_write_port<Instr>("EXECUTE_2_BRANCH" , Port::BW );
wp_writeback_datapath = make_write_port<Instr>("EXECUTE_2_WRITEBACK", Port::BW);
rp_datapath = make_read_port<Instr>("DECODE_2_EXECUTE", Port::LATENCY);
rp_trap = make_read_port<bool>("WRITEBACK_2_ALL_FLUSH", Port::LATENCY);

wp_long_latency_execution_unit = make_write_port<Instr>("EXECUTE_2_EXECUTE_LONG_LATENCY", PORT_BW);
wp_long_latency_execution_unit = make_write_port<Instr>("EXECUTE_2_EXECUTE_LONG_LATENCY", Port::BW);
rp_long_latency_execution_unit = make_read_port<Instr>("EXECUTE_2_EXECUTE_LONG_LATENCY", last_execution_stage_latency);

rp_flush = make_read_port<bool>("BRANCH_2_ALL_FLUSH", PORT_LATENCY);
rp_flush = make_read_port<bool>("BRANCH_2_ALL_FLUSH", Port::LATENCY);

rps_bypass[0].command_port = make_read_port<BypassCommand<Register>>("DECODE_2_EXECUTE_SRC1_COMMAND", PORT_LATENCY);
rps_bypass[1].command_port = make_read_port<BypassCommand<Register>>("DECODE_2_EXECUTE_SRC2_COMMAND", PORT_LATENCY);
rps_bypass[0].command_port = make_read_port<BypassCommand<Register>>("DECODE_2_EXECUTE_SRC1_COMMAND", Port::LATENCY);
rps_bypass[1].command_port = make_read_port<BypassCommand<Register>>("DECODE_2_EXECUTE_SRC2_COMMAND", Port::LATENCY);

wp_bypass = make_write_port<InstructionOutput>("EXECUTE_2_EXECUTE_BYPASS", PORT_BW);
wp_long_arithmetic_bypass = make_write_port<InstructionOutput>("EXECUTE_COMPLEX_ALU_2_EXECUTE_BYPASS", PORT_BW);
wp_bypass = make_write_port<InstructionOutput>("EXECUTE_2_EXECUTE_BYPASS", Port::BW);
wp_long_arithmetic_bypass = make_write_port<InstructionOutput>("EXECUTE_COMPLEX_ALU_2_EXECUTE_BYPASS", Port::BW);

rps_bypass[0].data_ports[0] = make_read_port<InstructionOutput>("EXECUTE_2_EXECUTE_BYPASS", PORT_LATENCY);
rps_bypass[1].data_ports[0] = make_read_port<InstructionOutput>("EXECUTE_2_EXECUTE_BYPASS", PORT_LATENCY);
rps_bypass[0].data_ports[0] = make_read_port<InstructionOutput>("EXECUTE_2_EXECUTE_BYPASS", Port::LATENCY);
rps_bypass[1].data_ports[0] = make_read_port<InstructionOutput>("EXECUTE_2_EXECUTE_BYPASS", Port::LATENCY);

rps_bypass[0].data_ports[1] = make_read_port<InstructionOutput>("EXECUTE_COMPLEX_ALU_2_EXECUTE_BYPASS", PORT_LATENCY);
rps_bypass[1].data_ports[1] = make_read_port<InstructionOutput>("EXECUTE_COMPLEX_ALU_2_EXECUTE_BYPASS", PORT_LATENCY);
rps_bypass[0].data_ports[1] = make_read_port<InstructionOutput>("EXECUTE_COMPLEX_ALU_2_EXECUTE_BYPASS", Port::LATENCY);
rps_bypass[1].data_ports[1] = make_read_port<InstructionOutput>("EXECUTE_COMPLEX_ALU_2_EXECUTE_BYPASS", Port::LATENCY);

rps_bypass[0].data_ports[2] = make_read_port<InstructionOutput>("MEMORY_2_EXECUTE_BYPASS", PORT_LATENCY);
rps_bypass[1].data_ports[2] = make_read_port<InstructionOutput>("MEMORY_2_EXECUTE_BYPASS", PORT_LATENCY);
rps_bypass[0].data_ports[2] = make_read_port<InstructionOutput>("MEMORY_2_EXECUTE_BYPASS", Port::LATENCY);
rps_bypass[1].data_ports[2] = make_read_port<InstructionOutput>("MEMORY_2_EXECUTE_BYPASS", Port::LATENCY);

rps_bypass[0].data_ports[3] = make_read_port<InstructionOutput>("WRITEBACK_2_EXECUTE_BYPASS", PORT_LATENCY);
rps_bypass[1].data_ports[3] = make_read_port<InstructionOutput>("WRITEBACK_2_EXECUTE_BYPASS", PORT_LATENCY);
rps_bypass[0].data_ports[3] = make_read_port<InstructionOutput>("WRITEBACK_2_EXECUTE_BYPASS", Port::LATENCY);
rps_bypass[1].data_ports[3] = make_read_port<InstructionOutput>("WRITEBACK_2_EXECUTE_BYPASS", Port::LATENCY);

rps_bypass[0].data_ports[4] = make_read_port<InstructionOutput>("BRANCH_2_EXECUTE_BYPASS", PORT_LATENCY);
rps_bypass[1].data_ports[4] = make_read_port<InstructionOutput>("BRANCH_2_EXECUTE_BYPASS", PORT_LATENCY);
rps_bypass[0].data_ports[4] = make_read_port<InstructionOutput>("BRANCH_2_EXECUTE_BYPASS", Port::LATENCY);
rps_bypass[1].data_ports[4] = make_read_port<InstructionOutput>("BRANCH_2_EXECUTE_BYPASS", Port::LATENCY);
}

template <typename FuncInstr>
Expand Down
30 changes: 15 additions & 15 deletions simulator/modules/fetch/fetch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18,30 +18,30 @@ namespace config {
template <typename FuncInstr>
Fetch<FuncInstr>::Fetch( Module* parent) : Module( parent, "fetch")
{
wp_datapath = make_write_port<Instr>("FETCH_2_DECODE", PORT_BW);
rp_stall = make_read_port<bool>("DECODE_2_FETCH_STALL", PORT_LATENCY);
wp_datapath = make_write_port<Instr>("FETCH_2_DECODE", Port::BW);
rp_stall = make_read_port<bool>("DECODE_2_FETCH_STALL", Port::LATENCY);

rp_flush_target = make_read_port<Target>("BRANCH_2_FETCH_TARGET", PORT_LATENCY);
rp_flush_target = make_read_port<Target>("BRANCH_2_FETCH_TARGET", Port::LATENCY);

wp_target = make_write_port<Target>("TARGET", PORT_BW);
rp_target = make_read_port<Target>("TARGET", PORT_LATENCY);
wp_target = make_write_port<Target>("TARGET", Port::BW);
rp_target = make_read_port<Target>("TARGET", Port::LATENCY);

wp_hold_pc = make_write_port<Target>("HOLD_PC", PORT_BW);
rp_hold_pc = make_read_port<Target>("HOLD_PC", PORT_LATENCY);
wp_hold_pc = make_write_port<Target>("HOLD_PC", Port::BW);
rp_hold_pc = make_read_port<Target>("HOLD_PC", Port::LATENCY);

rp_external_target = make_read_port<Target>("WRITEBACK_2_FETCH_TARGET", PORT_LATENCY);
rp_external_target = make_read_port<Target>("WRITEBACK_2_FETCH_TARGET", Port::LATENCY);

rp_bp_update = make_read_port<BPInterface>("BRANCH_2_FETCH", PORT_LATENCY);
rp_bp_update = make_read_port<BPInterface>("BRANCH_2_FETCH", Port::LATENCY);

wp_long_latency_pc_holder = make_write_port<Target>("LONG_LATENCY_PC_HOLDER", PORT_BW);
rp_long_latency_pc_holder = make_read_port<Target>("LONG_LATENCY_PC_HOLDER", PORT_LONG_LATENCY);
wp_long_latency_pc_holder = make_write_port<Target>("LONG_LATENCY_PC_HOLDER", Port::BW);
rp_long_latency_pc_holder = make_read_port<Target>("LONG_LATENCY_PC_HOLDER", Port::LONG_LATENCY);

wp_hit_or_miss = make_write_port<bool>("HIT_OR_MISS", PORT_BW);
rp_hit_or_miss = make_read_port<bool>("HIT_OR_MISS", PORT_LATENCY);
wp_hit_or_miss = make_write_port<bool>("HIT_OR_MISS", Port::BW);
rp_hit_or_miss = make_read_port<bool>("HIT_OR_MISS", Port::LATENCY);

/* port needed for handling misprediction at decode stage */
rp_bp_update_from_decode = make_read_port<BPInterface>("DECODE_2_FETCH", PORT_LATENCY);
rp_flush_target_from_decode = make_read_port<Target>("DECODE_2_FETCH_TARGET", PORT_LATENCY);
rp_bp_update_from_decode = make_read_port<BPInterface>("DECODE_2_FETCH", Port::LATENCY);
rp_flush_target_from_decode = make_read_port<Target>("DECODE_2_FETCH_TARGET", Port::LATENCY);

bp = BaseBP::create_configured_bp();
tags = CacheTagArray::create(
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