Fix interrupts register update condition

LLeny · Nov 10, 2024 · b63b1b1 · b63b1b1
1 parent 9aeaebf
commit b63b1b1
Showing 1 changed file with 6 additions and 7 deletions.
diff --git a/src/mikey/mod.rs b/src/mikey/mod.rs
@@ -144,10 +144,8 @@ impl Mikey {
 
         if int != 0 {
             int |= self.registers.data(INTSET);
-            trace!("INTSET -> {:02X}", int);
-            if !self.cpu.flags().contains(M6502Flags::I) {
-                self.registers.set_data(INTSET, int);
-            }            
+            self.registers.set_data(INTSET, int);
+            trace!("INTSET -> {:02X}", int);        
             if !bus.grant() { // wake up the cpu
                 bus.set_request(true);
             }
@@ -206,9 +204,10 @@ impl Mikey {
 
         match self.bus_owner {            
             MikeyBusOwner::Cpu => {
-                match self.registers.data(INTSET) {
-                    0 => self.cpu_pins.pin_off(M6502_IRQ),
-                    _ => self.cpu_pins.pin_on(M6502_IRQ),
+                if self.cpu.flags().contains(M6502Flags::I) || self.registers.data(INTSET) == 0 {
+                    self.cpu_pins.pin_off(M6502_IRQ);
+                } else {
+                    self.cpu_pins.pin_on(M6502_IRQ);
                 }
 
                 match bus.grant() {