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DE1_SoC_Audio_Example.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
+# Date created = 21:45:46  November 15, 2018
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.0"
+DATE = "21:45:46  November 15, 2018"
+
+# Revisions
+
+PROJECT_REVISION = "DE1_SoC_Audio_Example"

DE1_SoC_Audio_Example.qsf.bak

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
+# Date created = 21:45:46  November 15, 2018
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		DE1_SoC_Audio_Example_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY DE1_SoC_Audio_Example
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:45:46  NOVEMBER 15, 2018"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition"
+set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/avconf/I2C_Controller.v"
+set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/avconf/avconf.v"
+set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Audio_Controller.v"
+set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Audio_Clock.v"
+set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_SYNC_FIFO.v"
+set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_Clock_Edge.v"
+set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_Audio_Out_Serializer.v"
+set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_Audio_In_Deserializer.v"
+set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_Audio_Bit_Counter.v"
+set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/DE1_SoC_Audio_Example.v"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Display.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
+# Date created = 23:46:09  November 23, 2018
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.0"
+DATE = "23:46:09  November 23, 2018"
+
+# Revisions
+
+PROJECT_REVISION = "Display"