Updated migration LP

content/learning-paths/microcontrollers/project-migration-cmsis-v6/device_mapping.md

@@ -25,6 +25,9 @@ If you are using an Arm device from the CMSIS v5 pack, you need to switch the de
 | ARMCM85                                                    | ARMCM85 (PACBTI, MPU, DP_FPU, FP_MVE, DSP, TZ) |
 | ARMSC000                                                   | ARMSC000 (NO_FPU, NO_MPU) |
 | ARMSC300                                                   | ARMSC300 (NO_FPU, NO_MPU) |
+| ARMv8MBL                                                   | ARMCM23 (NO_FPU, MPU, TZ) |
+| ARMv8MML, ARMv8MML_DSP, ARMv8MML_SP, ARMv8MML_DSP_SP, ARMv8MML_DP, ARMv8MML_DSP_DP | ARMCM33 (SP_FPU, MPU, DSP, TZ) |
+| ARMv81MML_DSP_DP_MVE_FP                                    | ARMCM55 (DP_FPU, MPU, FP_MVE, DSP, TZ) |
 
 {{% notice %}}
 To reduce the functionality of the new device mappings, use the appropriate compiler flags. Please consult the toolchain manual for the compiler flags.

content/learning-paths/microcontrollers/project-migration-cmsis-v6/troubleshooting.md

@@ -8,7 +8,17 @@ layout: learningpathall
 
 ## Troubleshooting
 
-This section provides an overview of the most common errors you might encounter along with possible resolutions.
+This section provides an overview of the most common errors you might encounter along with possible resolutions. The following problems are explained:
+
+- [Missing device](#missing-device)
+- [Error instantiating RTE components](#error-instantiating-rte-components)
+- [Missing software components](#missing-software-components)
+- [Updating configuration files](#updating-configuration-files)
+- [Manual migration from Keil.ARM_Compiler pack](#manual-migration-from-keilarm_compiler-pack)
+- [Linker warning L6314W](#linker-warning-l6314w)
+- [Linker errors using the RTX5 library](#linker-errors-using-the-rtx5-library)
+- [Run-time exceptions due to wrong processor mode in RTX5](#run-time-exceptions-due-to-wrong-processor-mode-in-rtx5)
+
 
 ### Missing device
 
@@ -117,6 +127,28 @@ As the components from the Keil.ARM_Compiler pack do not have 1:1 replacements,
 All CMSIS-Compiler components require CMSIS-Compiler:Core to be present.
 {{% /notice %}}
 
+### Linker warning L6314W
+
+With CMSIS v6, a linker warning:
+
+```txt
+L6314W: No section matches pattern *(.bss.noinit)
+```
+
+now may get reported. This is due to the following entry in the Arm Compiler for Embedded scatter files:
+
+```txt
+RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+  *(.bss.noinit)
+}
+```
+
+This section is created for usage with [CMSIS-View's Event Recorder](https://arm-software.github.io/CMSIS-View/latest/evr.html), placing the event buffer in uninitialized memory so that it is persistent after a software reset.
+
+{{% notice Resolution %}}
+You can suppress the warning using the linker switch `--diag_suppress=L6314`.
+{{% /notice %}}
+
 ### Linker errors using the RTX5 library
 
 In CMSIS v5, the RTX5 libraries were built using the compiler options `-fshort-enums` and `-fshort-wchar`. In CMSIS v6, the default compiler options are different. If you are using the new libraries with old build settings, you will encounter the linker error `L6242W`:
@@ -137,3 +169,30 @@ In µVision, go to **Project - Options for Target** and click on the **C/C++ (AC
 {{% notice Note %}}
 If you are using libraries in your project that have been built with short enums/wchars (for example the MDK-Middleware), you need to use the RTX5 source code variant in your project as otherwise the linker will fail, even when unselecting the "Short enums/wchar" option.
 {{% /notice %}}
+
+### Run-time exceptions due to wrong processor mode in RTX5
+
+With the new Keil RTX5 v5.8.0, the default processor mode for thread execution has changed. Previously, it was:
+
+```c
+define OS_PRIVILEGE_MODE 1
+```
+
+which gave enabled the privileged mode for threads by default.
+
+The new default is:
+
+```c
+define OS_PRIVILEGE_MODE 0
+```
+
+which ends up in exceptions at run-time when threads use privileged operations.
+
+{{% notice Resolution %}}
+If an exception occurs at run-time, check the "Default Processor Mode for Thread execution" setting and adapt to "Privileged" if necessary.
+{{% /notice %}}
+
+{{% notice Note %}}
+Please note that you can also set the processor mode for threads individually (by setting the [osThreadPrivileged](https://arm-software.github.io/CMSIS_6/v6.0.0/RTOS2/group__CMSIS__RTOS__ThreadMgmt.html#ga7c2b7db42d23e4f56132e0ed739d02e5) define in the [osThread_Attr_t](https://arm-software.github.io/CMSIS_6/v6.0.0/RTOS2/group__CMSIS__RTOS__ThreadMgmt.html))
+{{% /notice %}}
+