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  1. ddr_bram_interface ddr_bram_interface Public

    SystemVerilog 3

  2. axi_ddr axi_ddr Public

    DDR4 with AXI4 interface RD & WR test

    VHDL 2

  3. DDR4-Naive-WR-RD DDR4-Naive-WR-RD Public

    SystemVerilog 1

  4. FM_ADD FM_ADD Public

    SystemVerilog 1

  5. chipyard chipyard Public

    Forked from ucb-bar/chipyard

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Scala

  6. DRAMsim3 DRAMsim3 Public

    Forked from umd-memsys/DRAMsim3

    DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

    C++

149 contributions in the last year

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Loading A graph representing GeorgeLin200100's contributions from March 03, 2024 to March 06, 2025. The contributions are 99% commits, 1% pull requests, 0% issues, 0% code review.   Code review   Issues 1% Pull requests 99% Commits

Contribution activity

March 2025

1 contribution in private repositories Mar 4
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