Start OSHWDem16 presentation

2016-10-28-Reset-ETSII-UPM/README.md

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-![](https://github.com/FPGAwars/workshops/raw/master/2016-10-28-Reset/wiki/Open-fpga-tools-01.png)
+![](https://github.com/FPGAwars/workshops/raw/master/2016-10-28-Reset-ETSII-UPM/wiki/Open-fpga-tools-01.png)
 
 # Reset ETSII UPM workshop
 

2016-11-05-OSHWDem16/.gitignore

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+*.sconsign.dblite
+*.asc
+*.bin
+*.rpt
+*.blif

2016-11-05-OSHWDem16/README.md

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+
+# OSHWDem16 workshop
+
+2016-11-05
+
+## Working on it ...
+
+## License
+
+![](https://github.com/FPGAwars/workshops/raw/master/wiki/attribution-share-alike-creative-commons-license.png)  
+[Creative Commons Attribution-ShareAlike 4.0 International License](http://creativecommons.org/licenses/by-sa/4.0/)

2016-11-05-OSHWDem16/examples/counter/counter.pcf

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+set_io leds[0] 95
+set_io leds[1] 96
+set_io leds[2] 97
+set_io leds[3] 98
+set_io leds[4] 99
+set_io clk 21

2016-11-05-OSHWDem16/examples/counter/counter.v

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+//-- Counter example
+
+module counter #(
+        parameter N = 29          //-- Counter bits lentgh
+  )(
+        input wire clk,
+        output wire [4:0] leds
+);
+
+reg [N-1:0] cont;
+reg rstn = 0;
+
+//-- Initialization
+always @(posedge clk)
+  rstn <= 1;
+
+//-- counter, with synchronous reset
+always @(posedge clk)
+  if (!rstn)
+    cont <= 0;
+  else
+    cont <= cont + 1;
+
+//-- Connect the 5 most significant bits to the leds
+assign leds = cont[N-1: N-6];
+
+endmodule

2016-11-05-OSHWDem16/examples/counter/counter_tb.v

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+//-- Testbench
+
+`default_nettype none
+`timescale 100 ns / 10 ns
+`define DUMPSTR(x) `"x.vcd`"
+
+
+module counter_tb();
+
+//-- Simulation time: 1us (10 * 100ns)
+parameter DURATION = 10;
+
+//-- Clock signal. It is not used in this simulation
+reg clk = 0;
+always #0.5 clk = ~clk;
+
+//-- Leds port
+wire [4:0] leds;
+
+//-- Counter bits length
+localparam N = 6;
+
+counter #(
+           .N(N)
+)  CONT0 (
+           .clk(clk),
+           .leds(leds)
+);
+
+initial begin
+  //-- File where to store the simulation
+  $dumpfile(`DUMPSTR(`VCD_OUTPUT));
+  $dumpvars(0, counter_tb);
+
+  #(DURATION) $display("END of the simulation");
+  $finish;
+end
+
+endmodule

2016-11-05-OSHWDem16/examples/leds/leds.pcf

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+set_io  LED0  95
+set_io  LED1  96
+set_io  LED2  97
+set_io  LED3  98
+set_io  LED4  99
+set_io  LED5  101
+set_io  LED6  102
+set_io  LED7  104

2016-11-05-OSHWDem16/examples/leds/leds.v

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+//-- Turn on all the leds
+
+module leds(output wire LED0,
+            output wire LED1,
+            output wire LED2,
+            output wire LED3,
+            output wire LED4,
+            output wire LED5,
+            output wire LED6,
+            output wire LED7);
+
+assign LED0 = 1'b1;
+assign LED1 = 1'b1;
+assign LED2 = 1'b1;
+assign LED3 = 1'b1;
+assign LED4 = 1'b1;
+assign LED5 = 1'b1;
+assign LED6 = 1'b1;
+assign LED7 = 1'b1;
+
+endmodule

2016-11-05-OSHWDem16/examples/leds/leds_tb.v

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+//-- Testbench
+
+`default_nettype none
+`define DUMPSTR(x) `"x.vcd`"
+`timescale 100 ns / 10 ns
+
+module leds_tb();
+
+//-- Simulation time: 1us (10 * 100ns)
+parameter DURATION = 10;
+
+//-- Clock signal. It is not used in this simulation
+reg clk = 0;
+always #0.5 clk = ~clk;
+
+//-- Leds port
+wire led0, led1, led2, led3, led4, led5, led6, led7;
+
+//-- Instantiate the unit to test
+leds UUT (
+           .LED0(led0),
+           .LED1(led1),
+           .LED2(led2),
+           .LED3(led3),
+           .LED4(led4),
+           .LED5(led5),
+           .LED6(led6),
+           .LED7(led7)
+         );
+
+
+initial begin
+
+  //-- File were to store the simulation results
+  $dumpfile(`DUMPSTR(`VCD_OUTPUT));
+  $dumpvars(0, leds_tb);
+
+   #(DURATION) $display("End of simulation");
+  $finish;
+end
+
+endmodule