FEXCore: Fixes the difference between CPL-0 and undefined instructions #3625
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@pmatos The clang-formatting github action isn't following the ignore patterns as expected for some reason. Looks like this path wasn't fully tested. |
Hummm... Not great. My apologies. Let me look at it first thing in the morning. |
Fixing this now. |
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alyssarosenzweig
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undefined instructions are expected to return SIGILL, while implemented instructions that aren't available in CPL-3 are expected to SIGSEGV. Noticed this while testing out CPU-Z, it installs a kernel module and does a bunch of `RDMSR` and `OUTS` instructions. Decided to walk through the rest of the instructions in the `System Instruction Reference` section. Turns out there's a bunch of oddities in there that we don't support. First step is to go through all the explicitl SIGILL and SIGSEGV and implement a test for them. Next step will be implementing the remaining operations that are considered "System" operations but are still available in CPL-3. This list includes: - lar - lgdt - lsl - sidt - sldt - stac - clac - verr - verw
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undefined instructions are expected to return SIGILL, while implemented
instructions that aren't available in CPL-3 are expected to SIGSEGV.
Noticed this while testing out CPU-Z, it installs a kernel module and
does a bunch of
RDMSRandOUTSinstructions. Decided to walk throughthe rest of the instructions in the
System Instruction Referencesection.
Turns out there's a bunch of oddities in there that we don't support.
First step is to go through all the explicitl SIGILL and SIGSEGV and
implement a test for them.
Next step will be implementing the remaining operations that are
considered "System" operations but are still available in CPL-3.
This list includes: