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OpcodeDispatcher: Fixes disabling TSO access on RSP SIB stores #3562

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merged 1 commit into from
Apr 11, 2024
+12 −7
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OpcodeDispatcher: Fixes disabling TSO access on RSP SIB stores #3562

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19 changes: 12 additions & 7 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4475,9 +4475,6 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X
auto Constant = _Constant(GPRSize * 8, Operand.Data.SIB.Scale);
Tmp = _Mul(IR::SizeToOpSize(GPRSize), Tmp, Constant);
}
if (Operand.Data.SIB.Index == FEXCore::X86State::REG_RSP && AccessType == MemoryAccessType::DEFAULT) {
AccessType = MemoryAccessType::NONTSO;
}
}

if (Operand.Data.SIB.Base != FEXCore::X86State::REG_INVALID) {
Expand All @@ -4489,10 +4486,6 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X
else {
Tmp = GPR;
}

if (Operand.Data.SIB.Base == FEXCore::X86State::REG_RSP && AccessType == MemoryAccessType::DEFAULT) {
AccessType = MemoryAccessType::NONTSO;
}
}
}

Expand All @@ -4513,6 +4506,12 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X
}
}

if ((Operand.Data.SIB.Base == FEXCore::X86State::REG_RSP ||
Operand.Data.SIB.Index == FEXCore::X86State::REG_RSP)
&& AccessType == MemoryAccessType::DEFAULT) {
AccessType = MemoryAccessType::NONTSO;
}

LoadableType = true;
}
else {
Expand Down Expand Up @@ -4762,6 +4761,12 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
MemStoreDst = _Bfe(IR::SizeToOpSize(std::max<uint8_t>(4u, AddrSize)), AddrSize * 8, 0, MemStoreDst);
}

if ((Operand.Data.SIB.Base == FEXCore::X86State::REG_RSP ||
Operand.Data.SIB.Index == FEXCore::X86State::REG_RSP)
&& AccessType == MemoryAccessType::DEFAULT) {
AccessType = MemoryAccessType::NONTSO;
}

MemStore = true;
}

Expand Down
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