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More patches towards shift rework #3557

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More patches towards shift rework #3557

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831346e
OpcodeDispatcher: calculate deferred flags before RMW on NZCV
alyssarosenzweig Apr 4, 2024
31522bc
OpcodeDispatcher: optimize shl flag
alyssarosenzweig Apr 5, 2024
56df669
unittests: add test for deferred flags + shift with cl=0
alyssarosenzweig Apr 4, 2024
77e0ba2
InstCountCI: Update
alyssarosenzweig Apr 5, 2024
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2 changes: 2 additions & 0 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1293,6 +1293,8 @@ friend class FEXCore::IR::PassManager;

// Set flag tracking to prepare for a read-modify-write operation on NZCV.
void HandleNZCV_RMW(uint32_t _PossiblySetNZCVBits = ~0) {
CalculateDeferredFlags();

if (NZCVDirty && CachedNZCV)
_StoreNZCV(CachedNZCV);

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2 changes: 1 addition & 1 deletion FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -587,7 +587,7 @@ void OpDispatchBuilder::CalculateFlags_ShiftLeft(uint8_t SrcSize, OrderedNode *R

// Extract the last bit shifted in to CF
auto Size = _Constant(SrcSize * 8);
auto ShiftAmt = _Sub(OpSize, Size, Src2);
auto ShiftAmt = SrcSize >= 4 ? _Neg(OpSize, Src2) : _Sub(OpSize, Size, Src2);
auto LastBit = _Lshr(OpSize, Src1, ShiftAmt);
SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(LastBit, 0, true);

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38 changes: 38 additions & 0 deletions unittests/ASM/FEX_bugs/nzcv_rmw.asm
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Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
%ifdef CONFIG
{
"RegData": {
"RAX": "0xcafe"
}
}
%endif

; FEX had a bug where an NZCV RMW would fail to calculate previously deferred
; flags, resulting in garbage flag values

; First zero NZCV and break visibility
mov rax, 0
add rax, 1
jz fexi_fexi_im_so_broken

jmp .begin
.begin:

; NZCV is zero. Set it to something nonzero with a deferred flag operation.
mov rax, 0
popcnt rax, rax

; Now do a variable shift that preserves flags. This would clear ZF if not for
; the condition on the shift flags.
mov rbx, 100
mov cl, 0
sar rbx, cl

; ZF should still be set.
jnz fexi_fexi_im_so_broken

mov rax, 0xcafe
hlt

fexi_fexi_im_so_broken:
mov rax, 0xdead
hlt
14 changes: 6 additions & 8 deletions unittests/InstructionCountCI/FlagM/PrimaryGroup.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1955,17 +1955,16 @@
]
},
"shl eax, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"lsl w22, w20, w21",
"mov x4, x22",
"cbz x21, #+0x24",
"cbz x21, #+0x20",
"tst w22, w22",
"mov w23, #0x20",
"sub w21, w23, w21",
"neg w21, w21",
"lsr w21, w20, w21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
Expand All @@ -1974,17 +1973,16 @@
]
},
"shl rax, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"lsl x22, x20, x21",
"mov x4, x22",
"cbz x21, #+0x24",
"cbz x21, #+0x20",
"tst x22, x22",
"mov w23, #0x40",
"sub x21, x23, x21",
"neg x21, x21",
"lsr x21, x20, x21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
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14 changes: 6 additions & 8 deletions unittests/InstructionCountCI/FlagM/Secondary.json
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Original file line number Diff line number Diff line change
Expand Up @@ -806,7 +806,7 @@
]
},
"shld eax, ebx, cl": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 20,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov w20, w7",
Expand All @@ -821,10 +821,9 @@
"csel x20, x21, x20, eq",
"mov w4, w20",
"msr nzcv, x23",
"cbz x22, #+0x24",
"cbz x22, #+0x20",
"tst w20, w20",
"mov w23, #0x20",
"sub w22, w23, w22",
"neg w22, w22",
"lsr w22, w21, w22",
"rmif x22, #63, #nzCv",
"mov x26, x20",
Expand All @@ -833,7 +832,7 @@
]
},
"shld rax, rbx, cl": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 19,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov x20, x4",
Expand All @@ -847,10 +846,9 @@
"csel x22, x20, x22, eq",
"mov x4, x22",
"msr nzcv, x23",
"cbz x21, #+0x24",
"cbz x21, #+0x20",
"tst x22, x22",
"mov w23, #0x40",
"sub x21, x23, x21",
"neg x21, x21",
"lsr x21, x20, x21",
"rmif x21, #63, #nzCv",
"mov x26, x22",
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14 changes: 6 additions & 8 deletions unittests/InstructionCountCI/PrimaryGroup.json
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Original file line number Diff line number Diff line change
Expand Up @@ -2401,17 +2401,16 @@
]
},
"shl eax, cl": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 16,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"lsl w22, w20, w21",
"mov x4, x22",
"cbz x21, #+0x34",
"cbz x21, #+0x30",
"tst w22, w22",
"mov w23, #0x20",
"sub w21, w23, w21",
"neg w21, w21",
"lsr w21, w20, w21",
"ubfx x21, x21, #0, #1",
"mrs x23, nzcv",
Expand All @@ -2424,17 +2423,16 @@
]
},
"shl rax, cl": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 16,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x5",
"lsl x22, x20, x21",
"mov x4, x22",
"cbz x21, #+0x34",
"cbz x21, #+0x30",
"tst x22, x22",
"mov w23, #0x40",
"sub x21, x23, x21",
"neg x21, x21",
"lsr x21, x20, x21",
"ubfx x21, x21, #0, #1",
"mrs x23, nzcv",
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14 changes: 6 additions & 8 deletions unittests/InstructionCountCI/Secondary.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1620,7 +1620,7 @@
]
},
"shld eax, ebx, cl": {
"ExpectedInstructionCount": 25,
"ExpectedInstructionCount": 24,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov w20, w7",
Expand All @@ -1635,10 +1635,9 @@
"csel x20, x21, x20, eq",
"mov w4, w20",
"msr nzcv, x23",
"cbz x22, #+0x34",
"cbz x22, #+0x30",
"tst w20, w20",
"mov w23, #0x20",
"sub w22, w23, w22",
"neg w22, w22",
"lsr w22, w21, w22",
"ubfx x22, x22, #0, #1",
"mrs x23, nzcv",
Expand All @@ -1651,7 +1650,7 @@
]
},
"shld rax, rbx, cl": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov x20, x4",
Expand All @@ -1665,10 +1664,9 @@
"csel x22, x20, x22, eq",
"mov x4, x22",
"msr nzcv, x23",
"cbz x21, #+0x34",
"cbz x21, #+0x30",
"tst x22, x22",
"mov w23, #0x40",
"sub x21, x23, x21",
"neg x21, x21",
"lsr x21, x20, x21",
"ubfx x21, x21, #0, #1",
"mrs x23, nzcv",
Expand Down
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