FEXCore: Moves CPUBackend definition internal

FEXCore/Source/Interface/Context/Context.cpp

@@ -66,4 +66,8 @@ namespace FEXCore::Context {
   FEXCore::CPUID::FunctionResults FEXCore::Context::ContextImpl::RunCPUIDFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) {
     return CPUID.RunFunctionName(Function, Leaf, CPU);
   }
+
+  bool FEXCore::Context::ContextImpl::IsAddressInCodeBuffer(FEXCore::Core::InternalThreadState *Thread, uintptr_t Address) const {
+    return Thread->CPUBackend->IsAddressInCodeBuffer(Address);
+  }
 }

FEXCore/Source/Interface/Context/Context.h

@@ -183,6 +183,9 @@ namespace FEXCore::Context {
       void MarkMemoryShared(FEXCore::Core::InternalThreadState *Thread) override;
 
       void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, fextl::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) override;
+
+      bool IsAddressInCodeBuffer(FEXCore::Core::InternalThreadState *Thread, uintptr_t Address) const override;
+
       // returns false if a handler was already registered
       CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void *Creator = nullptr, void *Data = nullptr);
 

FEXCore/Source/Interface/Core/CPUBackend.cpp

@@ -2,8 +2,8 @@
 #include "FEXCore/IR/IR.h"
 #include "FEXCore/Utils/AllocatorHooks.h"
 #include "Interface/Context/Context.h"
+#include "Interface/Core/CPUBackend.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
-#include <FEXCore/Core/CPUBackend.h>
 
 #ifndef _WIN32
 #include <sys/prctl.h>

FEXCore/Source/Interface/Core/Core.cpp

@@ -12,6 +12,7 @@ desc: Glues Frontend, OpDispatcher and IR Opts & Compilation, LookupCache, Dispa
 #include "Interface/Context/Context.h"
 #include "Interface/Core/ArchHelpers//Arm64Emitter.h"
 #include "Interface/Core/LookupCache.h"
+#include "Interface/Core/CPUBackend.h"
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/Frontend.h"
 #include "Interface/Core/ObjectCache/ObjectCacheService.h"
@@ -32,7 +33,6 @@ desc: Glues Frontend, OpDispatcher and IR Opts & Compilation, LookupCache, Dispa
 #include <FEXCore/Core/CodeLoader.h>
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/InternalThreadState.h>

FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h

@@ -2,8 +2,8 @@
 #pragma once
 
 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "Interface/Core/CPUBackend.h"
 
-#include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/fextl/memory.h>
 
 #ifdef VIXL_SIMULATOR

FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h

@@ -9,13 +9,13 @@ tags: backend|arm64
 
 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
 #include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
+#include "Interface/Core/CPUBackend.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 
 #include <aarch64/assembler-aarch64.h>
 #include <aarch64/disasm-aarch64.h>
 
 #include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/IR/RegisterAllocationData.h>

FEXCore/Source/Interface/Core/JIT/JITCore.h

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: MIT
 #pragma once
 
-#include <FEXCore/Core/CPUBackend.h>
+#include "Interface/Core/CPUBackend.h"
 #include <FEXCore/fextl/memory.h>
 
 namespace FEXCore::Context {

FEXCore/Source/Utils/ArchHelpers/Arm64.cpp

@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: MIT
 
+#include "Interface/Core/CPUBackend.h"
 #include "Utils/SpinWaitLock.h"
 
 #include <FEXCore/Debug/InternalThreadState.h>

FEXCore/include/FEXCore/Core/Context.h

@@ -235,6 +235,16 @@ namespace FEXCore::Context {
 
       FEX_DEFAULT_VISIBILITY virtual void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, fextl::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) = 0;
 
+      /**
+       * @brief Checks if a PC is inside of a thread's JIT code buffer.
+       *
+       * @param Thread Which thread's code buffers to check inside of.
+       * @param Address The PC to check against.
+       *
+       * @return true if PC is inside the thread's code buffers.
+       */
+      FEX_DEFAULT_VISIBILITY virtual bool IsAddressInCodeBuffer(FEXCore::Core::InternalThreadState *Thread, uintptr_t Address) const = 0;
+
       /**
        * @brief Allows the frontend to register its own thunk handlers independent of what is controlled in the backend.
        *

FEXCore/include/FEXCore/Core/CoreState.h

@@ -6,7 +6,6 @@
 #include <FEXCore/HLE/Linux/ThreadManagement.h>
 #include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/Telemetry.h>
-#include <FEXCore/Core/CPUBackend.h>
 
 #include <atomic>
 #include <cstddef>

FEXCore/include/FEXCore/Debug/InternalThreadState.h

@@ -2,7 +2,6 @@
 #pragma once
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/IR/RegisterAllocationData.h>
@@ -28,6 +27,7 @@ namespace FEXCore::Context {
 }
 
 namespace FEXCore::CPU {
+  class CPUBackend;
   union Relocation;
 }
 

Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator.cpp

@@ -1170,7 +1170,7 @@ namespace FEX::HLE {
     ++Thread->CurrentFrame->SignalHandlerRefCounter;
 
     uint64_t OldPC = ArchHelpers::Context::GetPc(ucontext);
-    const bool WasInJIT = Thread->CPUBackend->IsAddressInCodeBuffer(OldPC);
+    const bool WasInJIT = CTX->IsAddressInCodeBuffer(Thread, OldPC);
 
     // Spill the SRA regardless of signal handler type
     // We are going to be returning to the top of the dispatcher which will fill again
@@ -1312,7 +1312,7 @@ namespace FEX::HLE {
       // Store our thread state so we can come back to this
       StoreThreadState(Thread, Signal, ucontext);
 
-      if (Thread->CPUBackend->IsAddressInCodeBuffer(ArchHelpers::Context::GetPc(ucontext))) {
+      if (CTX->IsAddressInCodeBuffer(Thread, ArchHelpers::Context::GetPc(ucontext))) {
         // We are in jit, SRA must be spilled
         ArchHelpers::Context::SetPc(ucontext, Config.ThreadPauseHandlerAddressSpillSRA);
       } else {
@@ -1343,7 +1343,7 @@ namespace FEX::HLE {
       Thread->CurrentFrame->SignalHandlerRefCounter = 0;
 
       // Set the new PC
-      if (Thread->CPUBackend->IsAddressInCodeBuffer(ArchHelpers::Context::GetPc(ucontext))) {
+      if (CTX->IsAddressInCodeBuffer(Thread, ArchHelpers::Context::GetPc(ucontext))) {
         // We are in jit, SRA must be spilled
         ArchHelpers::Context::SetPc(ucontext, Config.ThreadStopHandlerAddressSpillSRA);
       } else {
@@ -1767,7 +1767,7 @@ namespace FEX::HLE {
     // Register SIGBUS signal handler.
     const auto SigbusHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *_info, void *ucontext) -> bool {
       const auto PC = ArchHelpers::Context::GetPc(ucontext);
-      if (!Thread->CPUBackend->IsAddressInCodeBuffer(PC)) {
+      if (!Thread->CTX->IsAddressInCodeBuffer(Thread, PC)) {
         // Wasn't a sigbus in JIT code
         return false;
       }

Source/Tools/TestHarnessRunner/TestHarnessRunner.cpp

@@ -22,7 +22,6 @@ desc: Used to run Assembly tests
 #include "TestHarnessRunner/HostRunner.h"
 
 #include <FEXCore/Config/Config.h>
-#include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/HostFeatures.h>
@@ -141,7 +140,7 @@ namespace LongJumpHandler {
     switch (ExceptionInfo->ExceptionRecord->ExceptionCode) {
       case STATUS_DATATYPE_MISALIGNMENT: {
         const auto PC = FEX::ArchHelpers::Context::GetPc(Context);
-        if (!Thread->CPUBackend->IsAddressInCodeBuffer(PC)) {
+        if (!Thread->CTX->IsAddressInCodeBuffer(Thread, PC)) {
           // Wasn't a sigbus in JIT code
           return EXCEPTION_CONTINUE_SEARCH;
         }

Source/Tools/TestHarnessRunner/TestHarnessRunner/HostRunner.cpp

@@ -2,7 +2,6 @@
 #include "ArchHelpers/UContext.h"
 #include "LinuxSyscalls/SignalDelegator.h"
 #include <FEXCore/Config/Config.h>
-#include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/X86Enums.h>

Source/Windows/WOW64/Module.cpp

@@ -116,7 +116,8 @@ namespace {
   }
 
   bool IsAddressInJit(uint64_t Address) {
-    return GetTLS().ThreadState()->CPUBackend->IsAddressInCodeBuffer(Address);
+    auto Thread = GetTLS().ThreadState();
+    return Thread->CTX->IsAddressInCodeBuffer(Thread, Address);
   }
 }
 
@@ -266,12 +267,13 @@ namespace Context {
   }
 
   bool HandleUnalignedAccess(CONTEXT *Context) {
-    if (!GetTLS().ThreadState()->CPUBackend->IsAddressInCodeBuffer(Context->Pc)) {
+    auto Thread = GetTLS().ThreadState();
+    if (!Thread->CTX->IsAddressInCodeBuffer(Thread, Context->Pc)) {
       return false;
     }
 
     FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
-    const auto Result = FEXCore::ArchHelpers::Arm64::HandleUnalignedAccess(GetTLS().ThreadState(), ParanoidTSO(), Context->Pc, &Context->X0);
+    const auto Result = FEXCore::ArchHelpers::Arm64::HandleUnalignedAccess(Thread, ParanoidTSO(), Context->Pc, &Context->X0);
     if (!Result.first) {
       return false;
     }