Skip to content

Commit

Permalink
InstCountCI: Update
Browse files Browse the repository at this point in the history 
Signed-off-by: Alyssa Rosenzweig <[email protected]>
  • Loading branch information
@alyssarosenzweig
alyssarosenzweig committed Jan 23, 2024
1 parent 4b211b3 commit c399f48
Show file tree
Hide file tree
Showing 12 changed files with 188 additions and 325 deletions.
15 changes: 5 additions & 10 deletions unittests/InstructionCountCI/FlagM/H0F38.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,28 +12,23 @@
},
"Instructions": {
"ptest xmm0, xmm1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 12,
"Comment": [
"0x66 0x0f 0x38 0x17"
],
"ExpectedArm64ASM": [
"and v2.16b, v16.16b, v17.16b",
"bic v3.16b, v17.16b, v16.16b",
"cnt v2.16b, v2.16b",
"cnt v3.16b, v3.16b",
"addv h2, v2.8h",
"addv h3, v3.8h",
"umaxv h2, v2.8h",
"umaxv h3, v3.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"msr nzcv, x20"
"tst w20, w20",
"rmif x21, #63, #NzCv"
]
},
"adcx eax, ebx": {
Expand Down
20 changes: 8 additions & 12 deletions unittests/InstructionCountCI/FlagM/PrimaryGroup.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1431,13 +1431,12 @@
]
},
"rcl al, 1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd0 /2",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, hs",
"lsl w22, w20, #1",
"orr w21, w22, w21",
"orr w21, w21, w20, lsl #1",
"bfxil x4, x21, #0, #8",
"rmif x20, #6, #nzCv",
"eor w20, w21, w20",
Expand Down Expand Up @@ -1567,40 +1566,37 @@
]
},
"rcl ax, 1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd1 /2",
"ExpectedArm64ASM": [
"uxth w20, w4",
"cset w21, hs",
"lsl w22, w20, #1",
"orr w21, w22, w21",
"orr w21, w21, w20, lsl #1",
"bfxil x4, x21, #0, #16",
"rmif x20, #14, #nzCv",
"eor w20, w21, w20",
"rmif x20, #15, #nzcV"
]
},
"rcl eax, 1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /2",
"ExpectedArm64ASM": [
"mov w20, w4",
"cset w21, hs",
"lsl w22, w20, #1",
"orr w4, w22, w21",
"orr w4, w21, w20, lsl #1",
"rmif x20, #30, #nzCv",
"eor w20, w4, w20",
"rmif x20, #31, #nzcV"
]
},
"rcl rax, 1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /2",
"ExpectedArm64ASM": [
"mov x20, x4",
"cset w21, hs",
"lsl x22, x20, #1",
"orr x4, x22, x21",
"orr x4, x21, x20, lsl #1",
"rmif x20, #62, #nzCv",
"eor x20, x4, x20",
"rmif x20, #63, #nzcV"
Expand Down
21 changes: 8 additions & 13 deletions unittests/InstructionCountCI/FlagM/Secondary.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -779,13 +779,12 @@
]
},
"shld ax, bx, cl": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"uxtb w22, w5",
"and x22, x22, #0x1f",
"and x22, x5, #0x1f",
"mov w23, #0x10",
"sub x23, x23, x22",
"lsl x24, x21, x22",
Expand All @@ -809,15 +808,13 @@
]
},
"shld eax, ebx, cl": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 22,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"uxtb w22, w5",
"and x22, x22, #0x1f",
"mov w23, #0x20",
"sub x23, x23, x22",
"and x22, x5, #0x1f",
"neg x23, x22",
"lsl x24, x21, x22",
"lsr w20, w20, w23",
"orr x20, x24, x20",
Expand All @@ -839,14 +836,12 @@
]
},
"shld rax, rbx, cl": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov x20, x4",
"uxtb w21, w5",
"and x21, x21, #0x3f",
"mov w22, #0x40",
"sub x22, x22, x21",
"and x21, x5, #0x3f",
"neg x22, x21",
"lsl x23, x20, x21",
"lsr x22, x7, x22",
"orr x22, x23, x22",
Expand Down
27 changes: 9 additions & 18 deletions unittests/InstructionCountCI/FlagM/Secondary_REP.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@
},
"Instructions": {
"popcnt ax, bx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 9,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"uxth w20, w7",
Expand All @@ -23,45 +23,36 @@
"addp v0.8b, v0.8b, v0.8b",
"umov w20, v0.b[0]",
"bfxil x4, x20, #0, #16",
"tst w20, w20",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"mov w26, #0x1"
]
},
"popcnt eax, ebx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"mov w20, w7",
"fmov s0, w20",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"tst w4, w4",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x4, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"mov w26, #0x1"
]
},
"popcnt rax, rbx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"fmov d0, x7",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"tst w4, w4",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x4, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"mov w26, #0x1"
]
},
"tzcnt ax, bx": {
Expand Down
98 changes: 34 additions & 64 deletions unittests/InstructionCountCI/FlagM/VEX_map2.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -164,61 +164,43 @@
]
},
"vptest xmm0, xmm1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b01 0x16 128-bit"
],
"ExpectedArm64ASM": [
"and v2.16b, v16.16b, v17.16b",
"bic v3.16b, v17.16b, v16.16b",
"cnt v2.16b, v2.16b",
"cnt v3.16b, v3.16b",
"addv h2, v2.8h",
"addv h3, v3.8h",
"umaxv h2, v2.8h",
"umaxv h3, v3.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"msr nzcv, x20"
"tst w20, w20",
"rmif x21, #63, #NzCv"
]
},
"vptest ymm0, ymm1": {
"ExpectedInstructionCount": 25,
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b01 0x16 256-bit"
],
"ExpectedArm64ASM": [
"and z2.d, z16.d, z17.d",
"bic z3.d, z17.d, z16.d",
"cnt z2.b, p7/m, z2.b",
"cnt z3.b, p7/m, z3.b",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z2.d",
"addv h1, v2.8h",
"addv h0, v0.8h",
"add v2.8h, v0.8h, v1.8h",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z3.d",
"addv h1, v3.8h",
"addv h0, v0.8h",
"add v3.8h, v0.8h, v1.8h",
"umaxv h2, p7, z2.h",
"umaxv h3, p7, z3.h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"msr nzcv, x20"
"tst w20, w20",
"rmif x21, #63, #NzCv"
]
},
"vmaskmovps xmm0, xmm1, [rax]": {
Expand Down Expand Up @@ -544,55 +526,43 @@
]
},
"bextr eax, ebx, ecx": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b00 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w5",
"mov w22, #0x1f",
"uxtb w23, w21",
"lsr w20, w20, w23",
"mov w24, #0x0",
"cmp w23, #0x1f (31)",
"csel w20, w20, w24, ls",
"ubfx w21, w21, #8, #8",
"uxtb w20, w5",
"lsr w21, w7, w20",
"mov w22, #0x0",
"cmp w20, #0x1f (31)",
"csel w20, w21, w22, ls",
"ubfx w21, w5, #8, #8",
"mov x22, #0xffffffffffffffff",
"lsl w22, w22, w21",
"bic w22, w20, w22",
"cmp w21, #0x1f (31)",
"csel w21, w21, w22, ls",
"mov w22, #0x1",
"lsl w21, w22, w21",
"sub w21, w21, #0x1 (1)",
"and w4, w20, w21",
"cmp x4, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"csel w4, w22, w20, ls",
"tst w4, w4"
]
},
"bextr rax, rbx, rcx": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b00 0xf7 64-bit"
],
"ExpectedArm64ASM": [
"mov w20, #0x3f",
"uxtb x21, w5",
"lsr x22, x7, x21",
"mov w23, #0x0",
"uxtb x20, w5",
"lsr x21, x7, x20",
"mov w22, #0x0",
"cmp x20, #0x3f (63)",
"csel x20, x21, x22, ls",
"ubfx x21, x5, #8, #8",
"mov x22, #0xffffffffffffffff",
"lsl x22, x22, x21",
"bic x22, x20, x22",
"cmp x21, #0x3f (63)",
"csel x21, x22, x23, ls",
"ubfx x22, x5, #8, #8",
"cmp x22, #0x3f (63)",
"csel x20, x22, x20, ls",
"mov w22, #0x1",
"lsl x20, x22, x20",
"sub x20, x20, #0x1 (1)",
"and x4, x21, x20",
"cmp x4, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
"csel x4, x22, x20, ls",
"tst x4, x4"
]
}
}
Expand Down
Loading

0 comments on commit c399f48

Please sign in to comment.