Merge pull request #4368 from Sonicadvance1/more_pshufd

OpcodeDispatcher: Implements a few more pshufd masks
FEX-Emu · Feb 19, 2025 · beef9ee · beef9ee
2 parents 34a274d + ef28a6c
commit beef9ee
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Showing 3 changed files with 302 additions and 242 deletions.
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -967,13 +967,17 @@ Ref OpDispatchBuilder::Single128Bit4ByteVectorShuffle(Ref Src, uint8_t Shuffle)
     // Special case element duplicate and broadcast to low or high 64-bits.
     return _VDupElement(OpSize::i128Bit, OpSize::i32Bit, Src, Shuffle & 0b11);
   }
-
   case 0b00'00'10'10: {
     // Weird reverse low elements and broadcast to each half of the register
     Ref Tmp = _VUnZip(OpSize::i128Bit, OpSize::i32Bit, Src, Src);
     Tmp = _VRev64(OpSize::i128Bit, OpSize::i32Bit, Tmp);
     return _VZip(OpSize::i128Bit, OpSize::i32Bit, Tmp, Tmp);
   }
+  case 0b00'00'11'10: {
+    // First element duplicated and shifted in to the top.
+    auto Dup = _VDupElement(OpSize::i128Bit, OpSize::i32Bit, Src, 0);
+    return _VExtr(OpSize::i128Bit, OpSize::i32Bit, Dup, Src, 2);
+  }
   case 0b00'01'00'01: {
     ///< Weird reversed low elements and broadcast
     Ref Tmp = _VRev64(OpSize::i128Bit, OpSize::i32Bit, Src);
@@ -984,6 +988,11 @@ Ref OpDispatchBuilder::Single128Bit4ByteVectorShuffle(Ref Src, uint8_t Shuffle)
     Ref Tmp = _VZip(OpSize::i128Bit, OpSize::i32Bit, Src, Src);
     return _VExtr(OpSize::i128Bit, OpSize::i8Bit, Tmp, Tmp, 4);
   }
+  case 0b00'01'10'11: {
+    // Inverse elements
+    Ref Tmp = _VRev64(OpSize::i128Bit, OpSize::i32Bit, Src);
+    return _VExtr(OpSize::i128Bit, OpSize::i32Bit, Tmp, Tmp, 2);
+  }
   case 0b00'10'00'10: {
     ///< Weird reversed even elements and broadcast
     Ref Tmp = _VUnZip(OpSize::i128Bit, OpSize::i32Bit, Src, Src);
@@ -1102,6 +1111,10 @@ Ref OpDispatchBuilder::Single128Bit4ByteVectorShuffle(Ref Src, uint8_t Shuffle)
     Ref Tmp = _VZip2(OpSize::i128Bit, OpSize::i32Bit, Src, Src);
     return _VExtr(OpSize::i128Bit, OpSize::i8Bit, Tmp, Tmp, 8);
   }
+  case 0b10'11'00'01: {
+    // Reverse each 64-bit lane.
+    return _VRev64(OpSize::i128Bit, OpSize::i32Bit, Src);
+  }
   case 0b10'11'10'11: {
     ///< Weird top two elements reverse and broadcast
     Ref Tmp = _VZip2(OpSize::i128Bit, OpSize::i64Bit, Src, Src);