OpcodeDispatcher: Assert on invalid size to LoadRegCachePair

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FEX-Emu · Jan 3, 2025 · afb92ff · afb92ff
1 parent 0beb71d
commit afb92ff
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Showing 2 changed files with 2 additions and 1 deletion.
diff --git a/FEXCore/Source/Interface/Core/JIT/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/JIT.cpp
@@ -820,7 +820,7 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size
       const auto ID = IR->GetID(CodeNode);
       switch (IROp->Op) {
 #define REGISTER_OP_RT(op, x) \
-  case FEXCore::IR::IROps::OP_##op: std::invoke(RT_##x, this, IROp, ID); break
+  case FEXCore::IR::IROps::OP_##op: (this->*RT_##x)(IROp, ID); break
 #define REGISTER_OP(op, x) \
   case FEXCore::IR::IROps::OP_##op: Op_##x(IROp, ID); break
 

diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
@@ -1948,6 +1948,7 @@ class OpDispatchBuilder final : public IREmitter {
 
   RefPair LoadRegCachePair(uint64_t Offset, uint8_t Index, RegisterClassType RegClass, IR::OpSize Size) {
     LOGMAN_THROW_AA_FMT(Index != DFIndex, "must be pairable");
+    LOGMAN_THROW_AA_FMT(Size != IR::OpSize::iUnsized, "Invalid size!");
 
     // Try to load a pair into the cache
     uint64_t Bits = (3ull << (uint64_t)Index);