InstCountCI: Update

Signed-off-by: Alyssa Rosenzweig <[email protected]>
FEX-Emu · Jan 23, 2024 · af7796b · af7796b
1 parent d049c91
commit af7796b
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Showing 12 changed files with 248 additions and 437 deletions.
diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json
@@ -12,28 +12,23 @@
   },
   "Instructions": {
     "ptest xmm0, xmm1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 12,
       "Comment": [
         "0x66 0x0f 0x38 0x17"
       ],
       "ExpectedArm64ASM": [
         "and v2.16b, v16.16b, v17.16b",
         "bic v3.16b, v17.16b, v16.16b",
-        "cnt v2.16b, v2.16b",
-        "cnt v3.16b, v3.16b",
-        "addv h2, v2.8h",
-        "addv h3, v3.8h",
+        "umaxv h2, v2.8h",
+        "umaxv h3, v3.8h",
         "umov w20, v2.h[0]",
         "umov w21, v3.h[0]",
         "mov w27, #0x0",
         "mov w26, #0x1",
-        "cmp x20, #0x0 (0)",
-        "cset x20, eq",
         "cmp x21, #0x0 (0)",
         "cset x21, eq",
-        "lsl x20, x20, #30",
-        "orr w20, w20, w21, lsl #29",
-        "msr nzcv, x20"
+        "tst w20, w20",
+        "rmif x21, #63, #NzCv"
       ]
     },
     "adcx eax, ebx": {

diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
@@ -1431,13 +1431,12 @@
       ]
     },
     "rcl al, 1": {
-      "ExpectedInstructionCount": 8,
+      "ExpectedInstructionCount": 7,
       "Comment": "GROUP2 0xd0 /2",
       "ExpectedArm64ASM": [
         "uxtb w20, w4",
         "cset w21, hs",
-        "lsl w22, w20, #1",
-        "orr w21, w22, w21",
+        "orr w21, w21, w20, lsl #1",
         "bfxil x4, x21, #0, #8",
         "rmif x20, #6, #nzCv",
         "eor w20, w21, w20",
@@ -1567,40 +1566,37 @@
       ]
     },
     "rcl ax, 1": {
-      "ExpectedInstructionCount": 8,
+      "ExpectedInstructionCount": 7,
       "Comment": "GROUP2 0xd1 /2",
       "ExpectedArm64ASM": [
         "uxth w20, w4",
         "cset w21, hs",
-        "lsl w22, w20, #1",
-        "orr w21, w22, w21",
+        "orr w21, w21, w20, lsl #1",
         "bfxil x4, x21, #0, #16",
         "rmif x20, #14, #nzCv",
         "eor w20, w21, w20",
         "rmif x20, #15, #nzcV"
       ]
     },
     "rcl eax, 1": {
-      "ExpectedInstructionCount": 7,
+      "ExpectedInstructionCount": 6,
       "Comment": "GROUP2 0xd1 /2",
       "ExpectedArm64ASM": [
         "mov w20, w4",
         "cset w21, hs",
-        "lsl w22, w20, #1",
-        "orr w4, w22, w21",
+        "orr w4, w21, w20, lsl #1",
         "rmif x20, #30, #nzCv",
         "eor w20, w4, w20",
         "rmif x20, #31, #nzcV"
       ]
     },
     "rcl rax, 1": {
-      "ExpectedInstructionCount": 7,
+      "ExpectedInstructionCount": 6,
       "Comment": "GROUP2 0xd1 /2",
       "ExpectedArm64ASM": [
         "mov x20, x4",
         "cset w21, hs",
-        "lsl x22, x20, #1",
-        "orr x4, x22, x21",
+        "orr x4, x21, x20, lsl #1",
         "rmif x20, #62, #nzCv",
         "eor x20, x4, x20",
         "rmif x20, #63, #nzcV"

diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json
@@ -779,13 +779,12 @@
       ]
     },
     "shld ax, bx, cl": {
-      "ExpectedInstructionCount": 24,
+      "ExpectedInstructionCount": 23,
       "Comment": "0x0f 0xad",
       "ExpectedArm64ASM": [
         "uxth w20, w7",
         "uxth w21, w4",
-        "uxtb w22, w5",
-        "and x22, x22, #0x1f",
+        "and x22, x5, #0x1f",
         "mov w23, #0x10",
         "sub x23, x23, x22",
         "lsl x24, x21, x22",
@@ -809,15 +808,13 @@
       ]
     },
     "shld eax, ebx, cl": {
-      "ExpectedInstructionCount": 24,
+      "ExpectedInstructionCount": 22,
       "Comment": "0x0f 0xad",
       "ExpectedArm64ASM": [
         "mov w20, w7",
         "mov w21, w4",
-        "uxtb w22, w5",
-        "and x22, x22, #0x1f",
-        "mov w23, #0x20",
-        "sub x23, x23, x22",
+        "and x22, x5, #0x1f",
+        "neg x23, x22",
         "lsl x24, x21, x22",
         "lsr w20, w20, w23",
         "orr x20, x24, x20",
@@ -839,14 +836,12 @@
       ]
     },
     "shld rax, rbx, cl": {
-      "ExpectedInstructionCount": 22,
+      "ExpectedInstructionCount": 20,
       "Comment": "0x0f 0xad",
       "ExpectedArm64ASM": [
         "mov x20, x4",
-        "uxtb w21, w5",
-        "and x21, x21, #0x3f",
-        "mov w22, #0x40",
-        "sub x22, x22, x21",
+        "and x21, x5, #0x3f",
+        "neg x22, x21",
         "lsl x23, x20, x21",
         "lsr x22, x7, x22",
         "orr x22, x23, x22",

diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP.json b/unittests/InstructionCountCI/FlagM/Secondary_REP.json
@@ -14,7 +14,7 @@
   },
   "Instructions": {
     "popcnt ax, bx": {
-      "ExpectedInstructionCount": 12,
+      "ExpectedInstructionCount": 9,
       "Comment": "0xf3 0x0f 0xb8",
       "ExpectedArm64ASM": [
         "uxth w20, w7",
@@ -23,45 +23,36 @@
         "addp v0.8b, v0.8b, v0.8b",
         "umov w20, v0.b[0]",
         "bfxil x4, x20, #0, #16",
+        "tst w20, w20",
         "mov w27, #0x0",
-        "mov w26, #0x1",
-        "cmp x20, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "mov w26, #0x1"
       ]
     },
     "popcnt eax, ebx": {
-      "ExpectedInstructionCount": 11,
+      "ExpectedInstructionCount": 8,
       "Comment": "0xf3 0x0f 0xb8",
       "ExpectedArm64ASM": [
         "mov w20, w7",
         "fmov s0, w20",
         "cnt v0.8b, v0.8b",
         "addv b0, v0.8b",
         "umov w4, v0.b[0]",
+        "tst w4, w4",
         "mov w27, #0x0",
-        "mov w26, #0x1",
-        "cmp x4, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "mov w26, #0x1"
       ]
     },
     "popcnt rax, rbx": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 7,
       "Comment": "0xf3 0x0f 0xb8",
       "ExpectedArm64ASM": [
         "fmov d0, x7",
         "cnt v0.8b, v0.8b",
         "addv b0, v0.8b",
         "umov w4, v0.b[0]",
+        "tst w4, w4",
         "mov w27, #0x0",
-        "mov w26, #0x1",
-        "cmp x4, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "mov w26, #0x1"
       ]
     },
     "tzcnt ax, bx": {