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InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <[email protected]>
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@alyssarosenzweig
alyssarosenzweig committed Mar 31, 2024
1 parent b51dba9 commit ab5eb5d
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Showing 2 changed files with 136 additions and 172 deletions.
142 changes: 62 additions & 80 deletions unittests/InstructionCountCI/FlagM/PrimaryGroup.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1246,8 +1246,8 @@
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xd0 /0",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"bfi w20, w20, #8, #8",
"mov w20, w4",
"bfi w20, w4, #8, #8",
"bfi w20, w20, #16, #16",
"ror w20, w20, #31",
"bfxil x4, x20, #0, #8",
Expand All @@ -1260,8 +1260,8 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd0 /1",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"bfi w20, w20, #8, #8",
"mov w20, w4",
"bfi w20, w4, #8, #8",
"ror w20, w20, #1",
"bfxil x4, x20, #0, #8",
"rmif x20, #6, #nzCv",
Expand Down Expand Up @@ -1338,8 +1338,8 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd1 /0",
"ExpectedArm64ASM": [
"uxth w20, w4",
"bfi w20, w20, #16, #16",
"mov w20, w4",
"bfi w20, w4, #16, #16",
"ror w20, w20, #31",
"bfxil x4, x20, #0, #16",
"rmif x20, #63, #nzCv",
Expand All @@ -1348,11 +1348,10 @@
]
},
"rol eax, 1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xd1 /0",
"ExpectedArm64ASM": [
"mov w20, w4",
"ror w4, w20, #31",
"ror w4, w4, #31",
"rmif x4, #63, #nzCv",
"eor w20, w4, w4, lsr #31",
"rmif x20, #0, #nzcV"
Expand All @@ -1372,8 +1371,8 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd1 /1",
"ExpectedArm64ASM": [
"uxth w20, w4",
"bfi w20, w20, #16, #16",
"mov w20, w4",
"bfi w20, w4, #16, #16",
"ror w20, w20, #1",
"bfxil x4, x20, #0, #16",
"rmif x20, #14, #nzCv",
Expand All @@ -1382,11 +1381,10 @@
]
},
"ror eax, 1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xd1 /1",
"ExpectedArm64ASM": [
"mov w20, w4",
"ror w4, w20, #1",
"ror w4, w4, #1",
"rmif x4, #30, #nzCv",
"eor w20, w4, w4, lsr #1",
"rmif x20, #30, #nzcV"
Expand Down Expand Up @@ -1585,36 +1583,33 @@
]
},
"rol al, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd2 /0",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"and w21, w21, #0x1f",
"bfi w20, w20, #8, #8",
"and x20, x5, #0x1f",
"cbz x20, #+0x28",
"mov w20, w4",
"bfi w20, w4, #8, #8",
"bfi w20, w20, #16, #16",
"mov w22, #0x20",
"sub w22, w22, w21",
"ror w20, w20, w22",
"neg w21, w5",
"ror w20, w20, w21",
"bfxil x4, x20, #0, #8",
"cbz x21, #+0x10",
"rmif x20, #63, #nzCv",
"eor w20, w20, w20, lsr #7",
"rmif x20, #0, #nzcV"
]
},
"ror al, cl": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd2 /1",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"and w21, w21, #0x1f",
"bfi w20, w20, #8, #8",
"and x20, x5, #0x1f",
"cbz x20, #+0x24",
"mov w20, w4",
"bfi w20, w4, #8, #8",
"bfi w20, w20, #16, #16",
"ror w20, w20, w21",
"ror w20, w20, w5",
"bfxil x4, x20, #0, #8",
"cbz x21, #+0x10",
"rmif x20, #6, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x20, #6, #nzcV"
Expand Down Expand Up @@ -1733,96 +1728,83 @@
]
},
"rol ax, cl": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"and w21, w21, #0x1f",
"bfi w20, w20, #16, #16",
"mov w22, #0x20",
"sub w22, w22, w21",
"ror w20, w20, w22",
"and x20, x5, #0x1f",
"cbz x20, #+0x24",
"mov w20, w4",
"bfi w20, w4, #16, #16",
"neg w21, w5",
"ror w20, w20, w21",
"bfxil x4, x20, #0, #16",
"cbz x21, #+0x10",
"rmif x20, #63, #nzCv",
"eor w20, w20, w20, lsr #15",
"rmif x20, #0, #nzcV"
]
},
"rol eax, cl": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"and w21, w21, #0x1f",
"mov w22, #0x20",
"sub w22, w22, w21",
"ror w20, w20, w22",
"mov x4, x20",
"cbz x21, #+0x10",
"rmif x20, #63, #nzCv",
"eor w20, w20, w20, lsr #31",
"and x20, x5, #0x1f",
"cbz x20, #+0x18",
"neg w20, w5",
"ror w4, w4, w20",
"rmif x4, #63, #nzCv",
"eor w20, w4, w4, lsr #31",
"rmif x20, #0, #nzcV"
]
},
"rol rax, cl": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"mov w21, #0x40",
"sub x21, x21, x20",
"ror x21, x4, x21",
"mov x4, x21",
"cbz x20, #+0x10",
"rmif x21, #63, #nzCv",
"eor x20, x21, x21, lsr #63",
"cbz x20, #+0x18",
"neg x20, x5",
"ror x4, x4, x20",
"rmif x4, #63, #nzCv",
"eor x20, x4, x4, lsr #63",
"rmif x20, #0, #nzcV"
]
},
"ror ax, cl": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"and w21, w21, #0x1f",
"bfi w20, w20, #16, #16",
"ror w20, w20, w21",
"and x20, x5, #0x1f",
"cbz x20, #+0x20",
"mov w20, w4",
"bfi w20, w4, #16, #16",
"ror w20, w20, w5",
"bfxil x4, x20, #0, #16",
"cbz x21, #+0x10",
"rmif x20, #14, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x20, #14, #nzcV"
]
},
"ror eax, cl": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"and w21, w21, #0x1f",
"ror w20, w20, w21",
"mov x4, x20",
"cbz x21, #+0x10",
"rmif x20, #30, #nzCv",
"eor w20, w20, w20, lsr #1",
"and x20, x5, #0x1f",
"cbz x20, #+0x14",
"ror w4, w4, w5",
"rmif x4, #30, #nzCv",
"eor w20, w4, w4, lsr #1",
"rmif x20, #30, #nzcV"
]
},
"ror rax, cl": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"ror x21, x4, x20",
"mov x4, x21",
"cbz x20, #+0x10",
"rmif x21, #62, #nzCv",
"eor x20, x21, x21, lsr #1",
"cbz x20, #+0x14",
"ror x4, x4, x5",
"rmif x4, #62, #nzCv",
"eor x20, x4, x4, lsr #1",
"rmif x20, #62, #nzcV"
]
},
Expand Down
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