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InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <[email protected]>
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@alyssarosenzweig
alyssarosenzweig committed Jan 12, 2024
1 parent e8945df commit a3800fa
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Showing 2 changed files with 110 additions and 152 deletions.
159 changes: 66 additions & 93 deletions unittests/InstructionCountCI/FlagM/Secondary.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1026,79 +1026,67 @@
]
},
"cmpxchg cl, bl": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 14,
"ExpectedArm64ASM": [
"uxtb w20, w7",
"uxtb w21, w5",
"uxtb x22, w4",
"cmp x21, x22",
"csel x23, x22, x21, eq",
"cmp x21, x22",
"csel w20, w20, w21, eq",
"bfxil x4, x23, #0, #8",
"bfxil x5, x20, #0, #8",
"sub x26, x22, x23",
"eor w27, w22, w23",
"sub x26, x22, x21",
"eor w27, w22, w21",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"eor w20, w22, w23",
"eor w21, w26, w22",
"and w20, w21, w20",
"rmif x20, #7, #nzcV"
"eor w23, w22, w21",
"eor w22, w26, w22",
"and w22, w22, w23",
"rmif x22, #7, #nzcV",
"bfxil x4, x21, #0, #8",
"csel x20, x20, x21, eq",
"bfxil x5, x20, #0, #8"
]
},
"cmpxchg cx, bx": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 14,
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w5",
"uxth x22, w4",
"cmp x21, x22",
"csel x23, x22, x21, eq",
"cmp x21, x22",
"csel w20, w20, w21, eq",
"bfxil x4, x23, #0, #16",
"bfxil x5, x20, #0, #16",
"sub x26, x22, x23",
"eor w27, w22, w23",
"sub x26, x22, x21",
"eor w27, w22, w21",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"eor w20, w22, w23",
"eor w21, w26, w22",
"and w20, w21, w20",
"rmif x20, #15, #nzcV"
"eor w23, w22, w21",
"eor w22, w26, w22",
"and w22, w22, w23",
"rmif x22, #15, #nzcV",
"bfxil x4, x21, #0, #16",
"csel x20, x20, x21, eq",
"bfxil x5, x20, #0, #16"
]
},
"cmpxchg ecx, ebx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 9,
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w5",
"mov w22, w4",
"cmp x21, x22",
"csel x23, x22, x21, eq",
"cmp x21, x22",
"csel x5, x20, x5, eq",
"cmp x23, x22",
"sub x26, x22, x21",
"eor w27, w22, w21",
"cmp w22, w21",
"cfinv",
"csel x4, x4, x21, eq",
"sub x26, x22, x23",
"eor w27, w22, w23",
"cmp w22, w23",
"cfinv"
"csel x5, x20, x5, eq"
]
},
"cmpxchg rcx, rbx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"ExpectedArm64ASM": [
"mov x20, x4",
"cmp x5, x20",
"csel x4, x20, x5, eq",
"cmp x5, x20",
"csel x5, x7, x5, eq",
"sub x26, x20, x4",
"eor x27, x20, x4",
"cmp x20, x4",
"cfinv"
"mov x20, x5",
"sub x26, x4, x20",
"eor x27, x4, x20",
"cmp x4, x20",
"cfinv",
"mov x4, x20",
"csel x5, x7, x20, eq"
]
},
"cmpxchg [rax], rbx": {
Expand All @@ -1116,26 +1104,23 @@
]
},
"cmpxchg al, bl": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 14,
"Comment": "0x0f 0xb0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"uxtb w21, w4",
"uxtb x22, w4",
"cmp x21, x22",
"csel x23, x22, x21, eq",
"cmp x21, x22",
"csel w20, w20, w21, eq",
"bfxil x4, x23, #0, #8",
"bfxil x4, x20, #0, #8",
"sub x26, x22, x23",
"eor w27, w22, w23",
"sub x26, x22, x21",
"eor w27, w22, w21",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"eor w20, w22, w23",
"eor w21, w26, w22",
"and w20, w21, w20",
"rmif x20, #7, #nzcV"
"eor w23, w22, w21",
"eor w22, w26, w22",
"and w22, w22, w23",
"rmif x22, #7, #nzcV",
"bfxil x4, x21, #0, #8",
"csel x20, x20, x21, eq",
"bfxil x4, x20, #0, #8"
]
},
"cmpxchg [rax], bl": {
Expand All @@ -1159,26 +1144,23 @@
]
},
"cmpxchg ax, bx": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 14,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"uxth x22, w4",
"cmp x21, x22",
"csel x23, x22, x21, eq",
"cmp x21, x22",
"csel w20, w20, w21, eq",
"bfxil x4, x23, #0, #16",
"bfxil x4, x20, #0, #16",
"sub x26, x22, x23",
"eor w27, w22, w23",
"sub x26, x22, x21",
"eor w27, w22, w21",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"eor w20, w22, w23",
"eor w21, w26, w22",
"and w20, w21, w20",
"rmif x20, #15, #nzcV"
"eor w23, w22, w21",
"eor w22, w26, w22",
"and w22, w22, w23",
"rmif x22, #15, #nzcV",
"bfxil x4, x21, #0, #16",
"csel x20, x20, x21, eq",
"bfxil x4, x20, #0, #16"
]
},
"cmpxchg [rax], bx": {
Expand All @@ -1202,24 +1184,19 @@
]
},
"cmpxchg eax, ebx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov x21, x4",
"mov w22, w21",
"mov w23, w21",
"cmp x22, x23",
"csel x24, x23, x22, eq",
"cmp x22, x23",
"csel x20, x20, x21, eq",
"cmp x24, x23",
"sub x26, x23, x22",
"eor w27, w23, w22",
"cmp w23, w22",
"cfinv",
"csel x4, x21, x22, eq",
"mov x4, x20",
"sub x26, x23, x24",
"eor w27, w23, w24",
"cmp w23, w24",
"cfinv"
"csel x4, x20, x21, eq"
]
},
"cmpxchg [rax], ebx": {
Expand All @@ -1240,20 +1217,16 @@
]
},
"cmpxchg rax, rbx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov x20, x4",
"sub x26, x20, x20",
"mov w27, #0x0",
"cmp x20, x20",
"csel x21, x20, x20, eq",
"cmp x20, x20",
"csel x22, x7, x20, eq",
"mov x4, x21",
"mov x4, x22",
"sub x26, x20, x21",
"eor x27, x20, x21",
"cmp x20, x21",
"cfinv"
"cfinv",
"mov x4, x20",
"csel x4, x7, x20, eq"
]
},
"btr ax, bx": {
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