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OpcodeDispatcher: optimize blsmsk flags
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Signed-off-by: Alyssa Rosenzweig <[email protected]>
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alyssarosenzweig committed Jan 23, 2024
1 parent 84313b4 commit 836835b
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Showing 3 changed files with 33 additions and 33 deletions.
22 changes: 7 additions & 15 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1014,30 +1014,22 @@ void OpDispatchBuilder::CalculateFlags_BLSI(uint8_t SrcSize, OrderedNode *Src) {
}

void OpDispatchBuilder::CalculateFlags_BLSMSK(uint8_t SrcSize, OrderedNode *Result, OrderedNode *Src) {
// Now for the flags.

auto Zero = _Constant(0);
auto One = _Constant(1);

uint32_t FlagsMaskToZero =
(1U << X86State::RFLAG_ZF_RAW_LOC) |
(1U << X86State::RFLAG_OF_RAW_LOC);

ZeroMultipleFlags(FlagsMaskToZero);

// PF/AF undefined
_InvalidateFlags((1UL << X86State::RFLAG_PF_RAW_LOC) |
(1UL << X86State::RFLAG_AF_RAW_LOC));

// CF set according to the Src
auto Zero = _Constant(0);
auto One = _Constant(1);
auto CFOp = _Select(IR::COND_EQ, Src, Zero, One, Zero);
SetRFLAG<X86State::RFLAG_CF_RAW_LOC>(CFOp);

auto SFOp = _Bfe(SizeToOpSize(SrcSize), 1, (SrcSize * 8) - 1, Result);
SetRFLAG<X86State::RFLAG_SF_RAW_LOC>(SFOp);
// The output of BLSMSK is always nonzero, so TST will clear Z (along with C
// and O) while setting S.
SetNZ_ZeroCV(SrcSize, Result);
SetRFLAG<X86State::RFLAG_CF_RAW_LOC>(CFOp);
}

void OpDispatchBuilder::CalculateFlags_BLSR(uint8_t SrcSize, OrderedNode *Result, OrderedNode *Src) {
// Now for flags.
auto Zero = _Constant(0);
auto One = _Constant(1);

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24 changes: 14 additions & 10 deletions unittests/InstructionCountCI/FlagM/VEX_map_group.json
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@
]
},
"blsmsk eax, ebx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 13,
"Comment": [
"Map group 17 0b010 32-bit"
],
Expand All @@ -53,17 +53,19 @@
"sub x21, x20, #0x1 (1)",
"eor x21, x21, x20",
"mov w4, w21",
"mov w21, #0x50000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"mov w22, #0x50000000",
"mrs x23, nzcv",
"bic x22, x23, x22",
"cmp x20, #0x0 (0)",
"cset x20, ne",
"msr nzcv, x21",
"rmif x20, #63, #nzCv"
"cset x20, eq",
"msr nzcv, x22",
"rmif x20, #63, #nzCv",
"lsr w20, w21, #31",
"rmif x20, #61, #Nzcv"
]
},
"blsmsk rax, rbx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 11,
"Comment": [
"Map group 17 0b010 64-bit"
],
Expand All @@ -74,9 +76,11 @@
"mrs x21, nzcv",
"bic x20, x21, x20",
"cmp x7, #0x0 (0)",
"cset x21, ne",
"cset x21, eq",
"msr nzcv, x20",
"rmif x21, #63, #nzCv"
"rmif x21, #63, #nzCv",
"lsr x20, x4, #63",
"rmif x20, #61, #Nzcv"
]
},
"blsi eax, ebx": {
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20 changes: 12 additions & 8 deletions unittests/InstructionCountCI/VEX_map_group.json
Original file line number Diff line number Diff line change
Expand Up @@ -643,7 +643,7 @@
]
},
"blsmsk eax, ebx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 15,
"Comment": [
"Map group 17 0b010 32-bit"
],
Expand All @@ -652,19 +652,21 @@
"sub x21, x20, #0x1 (1)",
"eor x21, x21, x20",
"mov w4, w21",
"mov w21, #0x50000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"mov w22, #0x50000000",
"mrs x23, nzcv",
"bic x22, x23, x22",
"cmp x20, #0x0 (0)",
"cset x20, ne",
"mov w0, w21",
"cset x20, eq",
"mov w0, w22",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr w21, w21, #31",
"bfi w20, w21, #31, #1",
"msr nzcv, x20"
]
},
"blsmsk rax, rbx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 11,
"Comment": [
"Map group 17 0b010 64-bit"
],
Expand All @@ -675,8 +677,10 @@
"mrs x21, nzcv",
"bic x20, x21, x20",
"cmp x7, #0x0 (0)",
"cset x21, ne",
"cset x21, eq",
"bfi w20, w21, #29, #1",
"lsr x21, x4, #63",
"bfi w20, w21, #31, #1",
"msr nzcv, x20"
]
},
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