Merge pull request #3505 from Sonicadvance1/telemetry_noncanonical

Telemetry: Adds tracker for non-canonical memory access crash
FEX-Emu · Mar 27, 2024 · 7f90ca5 · 7f90ca5
2 parents 542f454 + cccf263
commit 7f90ca5
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Showing 19 changed files with 40 additions and 31 deletions.
diff --git a/FEXCore/Source/Utils/Telemetry.cpp b/FEXCore/Source/Utils/Telemetry.cpp
@@ -33,6 +33,7 @@ namespace FEXCore::Telemetry {
     "Uses 32-bit Segment SS",
     "Uses 32-bit Segment CS",
     "Uses 32-bit Segment DS",
+    "Non-Canonical 64-bit address access",
   };
 
   static bool Enabled {true};

diff --git a/FEXCore/include/FEXCore/Utils/Telemetry.h b/FEXCore/include/FEXCore/Utils/Telemetry.h
@@ -30,6 +30,7 @@ namespace FEXCore::Telemetry {
     TYPE_USES_32BIT_SEGMENT_SS,
     TYPE_USES_32BIT_SEGMENT_CS,
     TYPE_USES_32BIT_SEGMENT_DS,
+    TYPE_UNHANDLED_NONCANONICAL_ADDRESS,
     TYPE_LAST,
   };
 

diff --git a/Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator.cpp b/Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator.cpp
@@ -1567,6 +1567,11 @@ namespace FEX::HLE {
       // FEX is hard crashing at this point and won't hit regular shutdown routines.
       // Add the signal to the crash mask.
       CrashMask |= (1ULL << Signal);
+      if (Signal == SIGSEGV &&
+          reinterpret_cast<uint64_t>(SigInfo.si_addr) >= SyscallHandler::TASK_MAX_64BIT) {
+        // Tried accessing invalid non-canonical x86-64 address.
+        UnhandledNonCanonical = true;
+      }
       SaveTelemetry();
 #endif
 

diff --git a/Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator.h b/Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator.h
@@ -154,6 +154,7 @@ namespace FEX::HLE {
     FEX_CONFIG_OPT(Core, CORE);
     fextl::string const ApplicationName;
     FEXCORE_TELEMETRY_INIT(CrashMask, TYPE_CRASH_MASK);
+    FEXCORE_TELEMETRY_INIT(UnhandledNonCanonical, TYPE_UNHANDLED_NONCANONICAL_ADDRESS);
 
     enum DefaultBehaviour {
       DEFAULT_TERM,

diff --git a/Source/Tools/LinuxEmulation/LinuxSyscalls/Syscalls.h b/Source/Tools/LinuxEmulation/LinuxSyscalls/Syscalls.h
@@ -308,6 +308,8 @@ class SyscallHandler : public FEXCore::HLE::SyscallHandler, FEXCore::HLE::Source
   bool NeedXIDCheck() const { return NeedToCheckXID; }
   void DisableXIDCheck() { NeedToCheckXID = false; }
 
+  constexpr static uint64_t TASK_MAX_64BIT = (1ULL << 48);
+
 protected:
   SyscallHandler(FEXCore::Context::Context *_CTX, FEX::HLE::SignalDelegator *_SignalDelegation);
 

diff --git a/Source/Tools/LinuxEmulation/LinuxSyscalls/Syscalls/Thread.cpp b/Source/Tools/LinuxEmulation/LinuxSyscalls/Syscalls/Thread.cpp
@@ -449,19 +449,18 @@ namespace FEX::HLE {
 
     REGISTER_SYSCALL_IMPL_FLAGS(arch_prctl, SyscallFlags::DEFAULT,
       [](FEXCore::Core::CpuStateFrame *Frame, int code, unsigned long addr) -> uint64_t {
-      constexpr uint64_t TASK_MAX = (1ULL << 48); // 48-bits until we can query the host side VA sanely. AArch64 doesn't expose this in cpuinfo
       uint64_t Result{};
       switch (code) {
         case 0x1001: // ARCH_SET_GS
-          if (addr >= TASK_MAX) {
+          if (addr >= SyscallHandler::TASK_MAX_64BIT) {
             // Ignore a non-canonical address
             return -EPERM;
           }
           Frame->State.gs_cached = addr;
           Result = 0;
         break;
         case 0x1002: // ARCH_SET_FS
-          if (addr >= TASK_MAX) {
+          if (addr >= SyscallHandler::TASK_MAX_64BIT) {
             // Ignore a non-canonical address
             return -EPERM;
           }

diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json
@@ -55,7 +55,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2096]",
+        "ldr q2, [x28, #2112]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "unimplemented (Unimplemented)",
@@ -68,7 +68,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2096]",
+        "ldr q2, [x28, #2112]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "unimplemented (Unimplemented)",

diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json
@@ -1618,7 +1618,7 @@
       "Comment": "0x0f 0xd7",
       "ExpectedArm64ASM": [
         "ldr d2, [x28, #768]",
-        "ldr d3, [x28, #2208]",
+        "ldr d3, [x28, #2224]",
         "cmlt v2.16b, v2.16b, #0",
         "and v2.16b, v2.16b, v3.16b",
         "addp v2.16b, v2.16b, v2.16b",

diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
@@ -38,7 +38,7 @@
       "ExpectedInstructionCount": 7,
       "Comment": "0x66 0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2208]",
+        "ldr q2, [x28, #2224]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",

diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json
@@ -72,7 +72,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2208]",
+        "ldr q2, [x28, #2224]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",

diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json
@@ -624,7 +624,7 @@
         "0x66 0x0f 0x38 0x41"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #1984]",
+        "ldr q2, [x28, #2000]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",

diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json
@@ -315,7 +315,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2112]",
+        "ldr q2, [x28, #2128]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -325,7 +325,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2128]",
+        "ldr q2, [x28, #2144]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -344,7 +344,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2144]",
+        "ldr q2, [x28, #2160]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -364,7 +364,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2160]",
+        "ldr q2, [x28, #2176]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -383,7 +383,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2176]",
+        "ldr q2, [x28, #2192]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -393,7 +393,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2192]",
+        "ldr q2, [x28, #2208]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },

diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json
@@ -2909,7 +2909,7 @@
         "mov x0, x6",
         "mov x1, x20",
         "mov x2, x7",
-        "ldr x3, [x28, #2272]",
+        "ldr x3, [x28, #2288]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
@@ -2920,7 +2920,7 @@
         "mov x0, x6",
         "mov x1, x20",
         "mov x2, x7",
-        "ldr x3, [x28, #2288]",
+        "ldr x3, [x28, #2304]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
@@ -2981,7 +2981,7 @@
         "mov x0, x6",
         "mov x1, x20",
         "mov x2, x7",
-        "ldr x3, [x28, #2280]",
+        "ldr x3, [x28, #2296]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
@@ -2994,7 +2994,7 @@
         "mov x0, x6",
         "mov x1, x20",
         "mov x2, x7",
-        "ldr x3, [x28, #2296]",
+        "ldr x3, [x28, #2312]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",

diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json
@@ -646,7 +646,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #2080]",
+        "ldr q3, [x28, #2096]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -657,7 +657,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #2080]",
+        "ldr q3, [x28, #2096]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -3434,7 +3434,7 @@
       "Comment": "0x0f 0xd7",
       "ExpectedArm64ASM": [
         "ldr d2, [x28, #768]",
-        "ldr d3, [x28, #2208]",
+        "ldr d3, [x28, #2224]",
         "cmlt v2.16b, v2.16b, #0",
         "and v2.16b, v2.16b, v3.16b",
         "addp v2.16b, v2.16b, v2.16b",

diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json
@@ -1014,7 +1014,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0x66 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2048]",
+        "ldr q2, [x28, #2064]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.2d, v16.2d, v2.2d"
       ]
@@ -1070,7 +1070,7 @@
       "ExpectedInstructionCount": 7,
       "Comment": "0x66 0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2208]",
+        "ldr q2, [x28, #2224]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",

diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json
@@ -452,7 +452,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0xf2 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2016]",
+        "ldr q2, [x28, #2032]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.4s, v16.4s, v2.4s"
       ]

diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json
@@ -4338,7 +4338,7 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2048]",
+        "ldr q2, [x28, #2064]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.2d, v17.2d, v2.2d"
       ]
@@ -4361,7 +4361,7 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2016]",
+        "ldr q2, [x28, #2032]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.4s, v17.4s, v2.4s"
       ]
@@ -4498,7 +4498,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2208]",
+        "ldr q2, [x28, #2224]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",

diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json
@@ -1575,7 +1575,7 @@
         "Map 2 0b01 0x41 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #1984]",
+        "ldr q2, [x28, #2000]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",

diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json
@@ -4799,7 +4799,7 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2096]",
+        "ldr q2, [x28, #2112]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "unimplemented (Unimplemented)",
@@ -4812,7 +4812,7 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2096]",
+        "ldr q2, [x28, #2112]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "unimplemented (Unimplemented)",