Fixes some new glibc allocations that cropped up

I guess this was handled by brk things before.
FEX-Emu · Dec 28, 2023 · 5b26499 · 5b26499
1 parent fc73700
commit 5b26499
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Showing 6 changed files with 18 additions and 6 deletions.
diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
@@ -353,8 +353,10 @@ Arm64Emitter::Arm64Emitter(FEXCore::Context::ContextImpl *ctx, void* EmissionPtr
   // Only setup the disassembler if enabled.
   // vixl's decoder is expensive to setup.
   if (Disassemble()) {
+    DisasmBuffer = static_cast<char*>(FEXCore::Allocator::malloc(DISASM_BUFFER_SIZE));
+    Disasm = fextl::make_unique<vixl::aarch64::Disassembler>(DisasmBuffer, DISASM_BUFFER_SIZE);
     DisasmDecoder = fextl::make_unique<vixl::aarch64::Decoder>();
-    DisasmDecoder->AppendVisitor(&Disasm);
+    DisasmDecoder->AppendVisitor(Disasm.get());
   }
 #endif
 

diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
@@ -63,6 +63,14 @@ class Arm64Emitter : public FEXCore::ARMEmitter::Emitter {
 protected:
   Arm64Emitter(FEXCore::Context::ContextImpl *ctx, void* EmissionPtr = nullptr, size_t size = 0);
 
+  virtual ~Arm64Emitter() {
+#ifdef VIXL_DISASSEMBLER
+    if (DisasmBuffer) {
+      FEXCore::Allocator::free(DisasmBuffer);
+    }
+#endif
+  }
+
   FEXCore::Context::ContextImpl *EmitterCTX;
   vixl::aarch64::CPU CPU;
 
@@ -233,7 +241,9 @@ class Arm64Emitter : public FEXCore::ARMEmitter::Emitter {
 #endif
 
 #ifdef VIXL_DISASSEMBLER
-  vixl::aarch64::Disassembler Disasm;
+  char *DisasmBuffer{};
+  constexpr static int DISASM_BUFFER_SIZE {256};
+  fextl::unique_ptr<vixl::aarch64::Disassembler> Disasm;
   fextl::unique_ptr<vixl::aarch64::Decoder> DisasmDecoder;
 
   FEX_CONFIG_OPT(Disassemble, DISASSEMBLE);

diff --git a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
@@ -526,7 +526,7 @@ void Dispatcher::EmitDispatcher() {
     const auto DisasmEnd = GetCursorAddress<const vixl::aarch64::Instruction*>();
     for (auto PCToDecode = DisasmBegin; PCToDecode < DisasmEnd; PCToDecode += 4) {
       DisasmDecoder->Decode(PCToDecode);
-      auto Output = Disasm.GetOutput();
+      auto Output = Disasm->GetOutput();
       LogMan::Msg::IFmt("{}", Output);
     }
   }

diff --git a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h
@@ -43,7 +43,7 @@ class Dispatcher final : public Arm64Emitter {
   static fextl::unique_ptr<Dispatcher> Create(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config);
 
   Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &Config);
-  ~Dispatcher();
+  virtual ~Dispatcher();
 
   /**
    * @name Dispatch Helper functions

diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
@@ -881,7 +881,7 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
     LogMan::Msg::IFmt("Disassemble Begin");
     for (auto PCToDecode = DisasmBegin; PCToDecode < DisasmEnd; PCToDecode += 4) {
       DisasmDecoder->Decode(PCToDecode);
-      auto Output = Disasm.GetOutput();
+      auto Output = Disasm->GetOutput();
       LogMan::Msg::IFmt("{}", Output);
     }
     LogMan::Msg::IFmt("Disassemble End");

diff --git a/Source/Tools/LinuxEmulation/VDSO_Emulation.cpp b/Source/Tools/LinuxEmulation/VDSO_Emulation.cpp
@@ -362,7 +362,7 @@ namespace FEX::VDSO {
   }
 
   void LoadHostVDSO() {
-
+    FEXCore::Allocator::YesIKnowImNotSupposedToUseTheGlibcAllocator glibc;
     void *vdso = dlopen("linux-vdso.so.1", RTLD_LAZY | RTLD_LOCAL | RTLD_NOLOAD);
     if (!vdso) {
       vdso = dlopen("linux-gate.so.1", RTLD_LAZY | RTLD_LOCAL | RTLD_NOLOAD);