EECS 151/251A FPGA Project Skeleton for Fall 2024

Check out the Project Overview to see the specs.

Checkpoint 1: 3-Stage RISC-V (rv32ui) Processor Block Design Diagram

Checkpoint 2: Fully Functional 3-Stage RISC-V (rv32ui) Processor

Checkpoint 3: Branch Predictor using Branch History Table

Checkpoint 4: Processor Optimization

Resources:

• RISC-V ISA Manual (Sections 2.2 - 2.6)