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Updates functional requirements #10

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503a12d
Updates functional requirements
cchaine May 9, 2024
4cb93d8
Adds more functional requirements
cchaine May 9, 2024
39c8885
Adds traceability
cchaine May 9, 2024
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132 changes: 132 additions & 0 deletions config/traceability-matrix.csv
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Original file line number Diff line number Diff line change
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tb_ecap5_wbuart.idle.01
tb_ecap5_wbuart.idle.02
tb_ecap5_wbuart.idle.03
tb_ecap5_wbuart.idle.04;F_RESET_02
tb_ecap5_wbuart.idle.05;F_RESET_01;F_REGISTERS_01
tb_ecap5_wbuart.write_cr.01;F_RESET_03
tb_ecap5_wbuart.write_cr.02
tb_ecap5_wbuart.write_cr.03;F_REGISTERS_01
tb_ecap5_wbuart.write_txdr.01
tb_ecap5_wbuart.write_txdr.02
tb_ecap5_wbuart.write_txdr.03
tb_ecap5_wbuart.write_txdr.04;F_REGISTERS_01
tb_ecap5_wbuart.read_rxdr.01;F_UART_01;F_UART_02;F_UART_03
tb_ecap5_wbuart.read_rxdr.02
tb_ecap5_wbuart.read_rxdr.03;F_REGISTERS_01;F_READ_01;F_RECEIVE_02;F_RECEIVE_03
tb_ecap5_wbuart.rxoe.01
tb_ecap5_wbuart.rxoe.02
tb_ecap5_wbuart.rxoe.03;F_REGISTERS_01;F_READ_02;F_RECEIVE_ERROR_03
tb_ecap5_wbuart.pe.01
tb_ecap5_wbuart.pe.02;F_REGISTERS_01;F_READ_02;F_RECEIVE_ERROR_01
tb_ecap5_wbuart.fe.01
tb_ecap5_wbuart.fe.02;F_REGISTERS_01;F_READ_02;F_RECEIVE_ERROR_02
tb_ecap5_wbuart.full_duplex.01;F_UART_04
tb_ecap5_wbuart.full_duplex.02;F_UART_04
tb_ecap5_wbuart.full_duplex.03;F_REGISTERS_01;F_UART_04
tb_rx_frontend.idle.01
tb_rx_frontend.idle.02
tb_rx_frontend.valid.7N1_01
tb_rx_frontend.valid.7N1_02;F_UART_01;F_UART_02;F_RECEIVE_01
tb_rx_frontend.valid.7N1_03
tb_rx_frontend.valid.7N1_04;F_UART_02;F_UART_03;F_RECEIVE_02
tb_rx_frontend.valid.7N2_01
tb_rx_frontend.valid.7N2_02;F_UART_01;F_UART_02;F_RECEIVE_01
tb_rx_frontend.valid.7N2_03
tb_rx_frontend.valid.7N2_04;F_UART_02;F_UART_03;F_RECEIVE_02
tb_rx_frontend.valid.7E1_01
tb_rx_frontend.valid.7E1_02;F_UART_01;F_UART_02;F_RECEIVE_01
tb_rx_frontend.valid.7E1_03
tb_rx_frontend.valid.7E1_04;F_UART_02;F_UART_03;F_RECEIVE_02
tb_rx_frontend.valid.7E2_01
tb_rx_frontend.valid.7E2_02;F_UART_01;F_UART_02;F_RECEIVE_01
tb_rx_frontend.valid.7E2_03
tb_rx_frontend.valid.7E2_04;F_UART_02;F_UART_03;F_RECEIVE_02
tb_rx_frontend.valid.7O1_01
tb_rx_frontend.valid.7O1_02;F_UART_01;F_UART_02;F_RECEIVE_01
tb_rx_frontend.valid.7O1_03
tb_rx_frontend.valid.7O1_04;F_UART_02;F_UART_03;F_RECEIVE_02
tb_rx_frontend.valid.7O2_01
tb_rx_frontend.valid.7O2_02;F_UART_01;F_UART_02;F_RECEIVE_01
tb_rx_frontend.valid.7O2_03
tb_rx_frontend.valid.7O2_04;F_UART_02;F_UART_03;F_RECEIVE_02
tb_rx_frontend.valid.8N1_01
tb_rx_frontend.valid.8N1_02;F_UART_01;F_UART_02;F_RECEIVE_01
tb_rx_frontend.valid.8N1_03
tb_rx_frontend.valid.8N1_04;F_UART_02;F_UART_03;F_RECEIVE_02
tb_rx_frontend.valid.8N2_01
tb_rx_frontend.valid.8N2_02;F_UART_01;F_UART_02;F_RECEIVE_01
tb_rx_frontend.valid.8N2_03
tb_rx_frontend.valid.8N2_04;F_UART_02;F_UART_03;F_RECEIVE_02
tb_rx_frontend.valid.8E1_01
tb_rx_frontend.valid.8E1_02;F_UART_01;F_UART_02;F_RECEIVE_01
tb_rx_frontend.valid.8E1_03
tb_rx_frontend.valid.8E1_04;F_UART_02;F_UART_03;F_RECEIVE_02
tb_rx_frontend.valid.8E2_01
tb_rx_frontend.valid.8E2_02;F_UART_01;F_UART_02;F_RECEIVE_01
tb_rx_frontend.valid.8E2_03
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tb_rx_frontend.valid.8O1_01
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tb_rx_frontend.valid.8O1_03
tb_rx_frontend.valid.8O1_04;F_UART_02;F_UART_03;F_RECEIVE_02
tb_rx_frontend.valid.8O2_01
tb_rx_frontend.valid.8O2_02;F_UART_01;F_UART_02;F_RECEIVE_01
tb_rx_frontend.valid.8O2_03
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tb_rx_frontend.baudrate.01
tb_rx_frontend.baudrate.02;F_UART_01;F_UART_02;F_RECEIVE_01
tb_rx_frontend.baudrate.03
tb_rx_frontend.baudrate.04;F_UART_02;F_UART_03;F_RECEIVE_02
tb_rx_frontend.parity.EVEN_01;F_RECEIVE_ERROR_01
tb_rx_frontend.parity.EVEN_02
tb_rx_frontend.parity.ODD_01;F_RECEIVE_ERROR_01
tb_rx_frontend.parity.ODD_02
tb_rx_frontend.framing.01
tb_rx_frontend.framing.02;F_RECEIVE_ERROR_02
tb_rx_frontend.framing.03
tb_tx_frontend.idle.01
tb_tx_frontend.idle.02
tb_tx_frontend.idle.03
tb_tx_frontend.7N1.01
tb_tx_frontend.7N1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7N1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7N2.01
tb_tx_frontend.7N2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7N2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7E1.01
tb_tx_frontend.7E1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7E1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7E2.01
tb_tx_frontend.7E2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7E2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7O1.01
tb_tx_frontend.7O1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7O1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7O2.01
tb_tx_frontend.7O2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7O2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8N1.01
tb_tx_frontend.8N1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8N1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8N2.01
tb_tx_frontend.8N2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8N2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8E1.01
tb_tx_frontend.8E1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8E1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8E2.01
tb_tx_frontend.8E2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8E2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8O1.01
tb_tx_frontend.8O1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8O1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8O2.01
tb_tx_frontend.8O2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8O2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.baudrate.01
tb_tx_frontend.baudrate.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.baudrate.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_wb_interface.read.01;I_MEMORY_INTERFACE_01
tb_wb_interface.read.02;I_MEMORY_INTERFACE_01
tb_wb_interface.write.01;I_MEMORY_INTERFACE_01
tb_wb_interface.write.02;I_MEMORY_INTERFACE_01
2 changes: 2 additions & 0 deletions docs/CMakeLists.txt
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Expand Up @@ -8,7 +8,9 @@ if(Sphinx_FOUND)
"${CMAKE_CURRENT_LIST_DIR}/src/_ext/requirement.py"
"${CMAKE_CURRENT_LIST_DIR}/src/_static/css/custom.css"
"${CMAKE_CURRENT_LIST_DIR}/src/assets/logo.svg"
"${CMAKE_CURRENT_LIST_DIR}/src/assets/favicon.ico"
"${CMAKE_CURRENT_LIST_DIR}/src/assets/architecture.svg"
"${CMAKE_CURRENT_LIST_DIR}/src/assets/uart.svg"
"${CMAKE_CURRENT_LIST_DIR}/src/guide/registers.rst"
"${CMAKE_CURRENT_LIST_DIR}/src/index.rst"
"${CMAKE_CURRENT_LIST_DIR}/src/spec/content/uart_sr.rst"
Expand Down
Binary file added docs/src/assets/favicon.ico
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187 changes: 187 additions & 0 deletions docs/src/assets/uart.drawio
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3 changes: 3 additions & 0 deletions docs/src/assets/uart.svg
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1 change: 1 addition & 0 deletions docs/src/conf.py
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Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@
html_css_files = [
'css/custom.css'
]
html_favicon = 'assets/favicon.ico'


todo_include_todos = True
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