A few fixes (some specific for 5A-75B)

README.md

@@ -1,19 +1,32 @@
-# `Colorlight 5A-75X Litex Ethernet Demo`
+# `Rust SoC Playground using LiteX, VexRiscV and the Colorlight 5A-75B board`
 
-> Litex SoC and Rust software for [Colorlight 5A-75X][colorlight] board as a simple Ethernet demo.
+This repository contains a lot of fun with rust and RiscV.
 
-This project is developed and maintained by [DerFetzer][team].
+The main branch is a small demo of a TCP connection with different options like turning LEDs on/off or registering an external button interrupt.
+It is somewhat ceaned up and meant for people who want to get started.
 
-## Usage
+Most of the instructions are adapted from https://github.com/DerFetzer/colorlight-litex and https://github.com/icebreaker-fpga/icebreaker-litex-examples:
 
 1. Install Litex as described [here][litex].
 2. Install [ecpprog][ecpprog].
 4. Connect a USB to JTAG adaptor to your board.
 5. Build and flash the SOC with something like the following:
 ```
-python soc/colorlight_5a_75x.py --build --flash --board=5a-75e --revision=6.0 --with-ethernet --sys-clk-freq 50e6 --use-internal-osc
+python3 colorlight_5a_75x.py  --flash --board=5a-75b --revision=7.0 --with-ethernet --sys-clk-freq 60e6
+
 ```
-4. Follow the instructions in [eth_demo][eth_demo] to build the software.
+4. Follow the instructions in [SoC_demo][SoC_demo] to build the software.
+
+
+There are a few things added to the standard Colorlight 5A-75B. If you just want to try the SoC with one onboard LED, the onboard button and just the TX of the UART you do not need to modify anything.
+
+
+Working in some branch:
+- Ethernet with smoltcp thanks to https://github.com/DerFetzer/colorlight-litex
+- Interrupts by staring a lot at https://github.com/betrusted-io/xous-core
+- A simple second order sigma-delta ADC using a CIC decimator
+- An IIR filter using on-chip sigma-delta ADC/DAC
+- A peltier temperature controller using a custom on-SoC ratiometric ADC, an IIR filter triggered by timer interrupts, TCP telemetry, UDP temperature set and the onboard line drivers in parallel as peltier drivers ;)
 
 ## Credits
 
@@ -26,4 +39,4 @@ and the Litex [target file][target] for the Colorlight board.
 [litex-example]: https://github.com/icebreaker-fpga/icebreaker-litex-examples
 [colorlight]: http://www.colorlight-led.com/product/colorlight-5a-75e-led-display-receiving-card.html
 [target]: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/colorlight_5a_75x.py
-[eth_demo]: rust/eth_demo/README.md 
+[SoC_demo]: rust/SoC_demo/README.md

python/recieve.py

@@ -0,0 +1,48 @@
+import socket
+import matplotlib.pyplot as plt
+import matplotlib.animation as animation
+import datetime as dt
+
+s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+s.connect(('192.168.1.50', 1234))
+
+msg = s.recv(4)
+s.close()
+val = int.from_bytes(msg, byteorder='big', signed=False)
+print([x for x in msg])
+print(val)
+
+fig = plt.figure()
+ax = fig.add_subplot(1, 1, 1)
+xs = []
+ys = []
+
+
+
+def animate(i, xs, ys):
+    s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+    s.connect(('192.168.1.50', 1234))
+    msg = s.recv(4)
+    s.close()
+    val = int.from_bytes(msg, byteorder='big', signed=False)
+    print([x for x in msg])
+    print(val)
+    xs.append(dt.datetime.now().strftime('%H:%M:%S.%f'))
+    ys.append(val)
+     # Limit x and y lists to 100 items
+    xs = xs[-200:]
+    ys = ys[-200:]
+
+    # Draw x and y lists
+    ax.clear()
+    ax.plot(xs, ys)
+
+    # Format plot
+    plt.xticks(rotation=45, ha='right')
+    plt.subplots_adjust(bottom=0.30)
+    plt.title('SoCstream')
+    plt.ylabel('Temperature')
+
+# Set up plot to call animate() function periodically
+ani = animation.FuncAnimation(fig, animate, fargs=(xs, ys), interval=500)
+plt.show()

python/recieve_test.py

@@ -0,0 +1,9 @@
+
+import socket
+
+s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+s.connect(('192.168.1.50', 1234))
+
+msg = s.recv(1024)
+
+print([x for x in msg])

rust/eth_demo/.cargo/flash.sh → rust/SoC_demo/.cargo/flash.sh

@@ -6,4 +6,4 @@ set -e
 riscv64-unknown-elf-objcopy $1 -O binary $1.bin
 
 # Program Colorlight
-ecpprog -o 0x00100000 $1.bin
+ecpprog -o 0x00100000 -d i:0x0403:0x6014:1 $1.bin

rust/eth_demo/Cargo.toml → rust/SoC_demo/Cargo.toml

@@ -1,14 +1,16 @@
 [package]
-name = "eth_demo"
+name = "temp_controller"
 version = "0.1.0"
-authors = ["Piotr Esden-Tempski <[email protected]>", "DerFetzer <[email protected]>"]
+authors = ["Piotr Esden-Tempski <[email protected]>", "DerFetzer <[email protected]>", "SingularitySurfer"]
 edition = "2018"
 
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [dependencies]
 litex-pac = { path = "../litex-pac" }
 riscv-rt  = "0.8.0"
+riscv = "0.6.0"
+vexriscv = "0.0.3"
 panic-halt = "0.2"
 log = "0.4.11"
 smoltcp = { version = "0.6", default-features = false, features = ["ethernet", "proto-ipv4", "socket-udp" ,"socket-tcp", "log"] }
@@ -22,4 +24,3 @@ debug = true
 # Improve code generation
 lto = true
 codegen-units = 1
-

rust/eth_demo/README.md → rust/SoC_demo/README.md

@@ -32,28 +32,22 @@ cargo run --release
 
 It might be necessary to reset the board with a power cycle or by loading the SOC bitstream again. 
 
-You now should have a TCP endpoint at `192.168.1.50:1234` and a UDP endpoint at `192.168.1.50:5678` listening for connections.
+You now should have a TCP endpoint at `192.168.1.50:1234`.
 
 Connect your computer to the board's Ethernet port an assign a static IP from the `192.168.1.0/24` subnet.
 
-You can now connect to the sockets and get a `Hello World!` back.
+You can now connect to the SoC using netcat:
 
 ```
-echo "" | netcat 192.168.1.50 1234
-echo "" | netcat -u 192.168.1.50 5678
-```
+rlwrap nc -vv 192.168.1.50 1234
 
-Connect a USB to UART adapter as described in [litex-boards][uart].
+```
 
-You should be able to access the console output by running the wishbone-tool.
+Now you should have a TCP connection with the SoC and you can talk to it. For example just type "hi" and press enter. Or "led on". If you press the button on the board, you should get a "button pressed" message via TCP. Have a look at main.rs to see which commands the SoC can parse.
 
-```
-wishbone-tool --uart /dev/ttyUSB1 -s terminal
-```
 
-You can find the wishbone-tool here: https://github.com/litex-hub/wishbone-utils
 
-NOTE: If you decided to build your SOC without the `--debug` parameter you can access the console output directly. For example using screen:
+NOTE: You can also look at the UART output. Just connect a UART probe to the correct pins (look at the custom pinout at the top of the LiteX SoC description). Example using screen:
 
 ```
 screen /dev/ttyUSB1 115200
@@ -63,4 +57,3 @@ To exit screen you can type `Ctrl-a k` or `Ctrl-a Ctrl-k`
 
 
 [bug]: https://github.com/rust-lang/cargo/issues/7915#issuecomment-683294870
-[uart]: https://github.com/litex-hub/litex-boards/blob/e4cdbe0f7ad0653e825556d992d233a1723273e3/litex_boards/targets/colorlight_5a_75x.py#L11

rust/SoC_demo/rust-project.json

@@ -0,0 +1,4 @@
+{
+    "rust.target": "riscv32imac-unknown-none-elf",
+    "rust.all_targets": false
+}

rust/SoC_demo/src/adc.rs

@@ -0,0 +1,16 @@
+use litex_pac::ADC;
+
+pub struct Adc {
+    registers: ADC,
+}
+
+#[allow(dead_code)]
+impl Adc {
+    pub fn new(registers: ADC) -> Self {
+        Self { registers }
+    }
+
+    pub fn read(&mut self) -> u32 {
+        self.registers.adc_value.read().bits()
+    }
+}

rust/SoC_demo/src/dac.rs

@@ -0,0 +1,18 @@
+use litex_pac::DAC;
+
+pub struct Dac {
+    registers: DAC,
+}
+
+#[allow(dead_code)]
+impl Dac {
+    pub fn new(registers: DAC) -> Self {
+        Self { registers }
+    }
+
+    pub fn set(&mut self, value: u32) {
+        unsafe{
+            self.registers.val.write(|w| w.bits(value));
+        }
+    }
+}

rust/SoC_demo/src/gpio.rs

@@ -0,0 +1,103 @@
+use litex_pac::GPIO;
+
+pub struct Gpio {
+    registers: GPIO,
+}
+
+#[allow(dead_code)]
+impl Gpio {
+    pub fn new(registers: GPIO) -> Self {
+        Self { registers }
+    }
+
+    pub fn status(&mut self) -> u32 {
+        self.registers.in_.read().bits()
+    }
+
+    pub fn set_interrupt_polarity(&mut self, pol: bool) {
+        unsafe {
+            if pol {
+                self.registers.polarity.write(|w| w.bits(1));
+            } else {
+                self.registers.polarity.write(|w| w.bits(0));
+            }
+        }
+    }
+
+    pub fn en_interrupt(&mut self) {
+        unsafe {
+            self.registers.ev_enable.write(|w| w.bits(0xFFFF_FFFF));
+        }
+    }
+
+    pub fn clr_interrupt(&mut self) {
+        unsafe {
+            self.registers.ev_pending.write(|w| w.bits(0xFFFF_FFFF));
+        }
+    }
+
+    pub fn dis_interrupt(&mut self) {
+        unsafe {
+            self.registers.ev_enable.write(|w| w.bits(0));
+        }
+    }
+
+}
+
+// pub struct Gpio2 {
+//     registers: GPIO2,
+// }
+//
+// #[allow(dead_code)]
+// impl Gpio2 {
+//
+//     pub fn new(registers: GPIO2) -> Self {
+//         Self { registers }
+//     }
+//
+//     pub fn status(&mut self) -> u32 {
+//         self.registers.in_.read().bits()
+//     }
+//
+//     pub fn set_interrupt_polarity(&mut self, pol: bool) {
+//         unsafe {
+//             if pol {
+//                 self.registers.polarity.write(|w| w.bits(1));
+//             }else {
+//                 self.registers.polarity.write(|w| w.bits(0));
+//             }
+//         }
+//     }
+//
+//     pub fn en_interrupt(&mut self) {
+//         unsafe {
+//
+//             self.registers.ev_enable.write(|w| w.bits(0xffff));
+//         }
+//     }
+//
+//     pub fn clr_interrupt(&mut self) {
+//         unsafe {
+//             self.registers.ev_pending.write(|w| w.bits(0xFFFF_FFFF));
+//         }
+//     }
+//
+//     pub fn dis_interrupt(&mut self) {
+//         unsafe {
+//             self.registers.ev_enable.write(|w| w.bits(0));
+//         }
+//     }
+//
+//     pub fn ev_pending(&mut self) -> u32 {
+//         self.registers.ev_pending.read().bits()
+//     }
+//
+//     pub fn ev_status(&mut self) -> u32 {
+//         self.registers.ev_status.read().bits()
+//     }
+//
+//     pub fn ev_enable(&mut self) -> u32 {
+//         self.registers.ev_enable.read().bits()
+//     }
+//
+// }