- Get the Image file from Here
- Untar
ZC702-2.6.0.tar.xz
- flash the image to sd card using balena etcher or dd
sudo dd bs=1M if=<image-name>.img of=/dev/<sdcard>
- Insert the SDCARD into the board
- ON ZC702 keep SW16 boot config switch position: 00110
- You can login to the board accessing the serial port
- Solve the jupyter access issue.
- There are two ways for network connection:
- Connect board to common router
- Connect board ethernet port directly to PC
- More Info Here
- I'm using the first option:
- First check whether the network port running on board using
ping 8.8.8.8
- Then run
ifconfig
and find out the address of eth0 inet. - On host computer
http://<etho0-address>:9090
- Ensure port 9090 is not blocked by your router/isp.
- Login with password
xilinx
- First check whether the network port running on board using
- There are two ways for network connection:
- PYNQ-DPU port on zc702
- Xilinx has a DPU library, it is directly supported to pynq boards via pynq-dpu repo and vitis AI.
- We will need to port it for ZC702.
- Reference TRD: Zynq-7000-DPU-TRD
- Figure out the way to include FPGA bit file on the board
- create a
test_repo/ZC702
folder inside<pynq>/sdbuild
- The
test_repo/ZC702
should contain the ZC702 BSP file which can be downloaded from the xilinx site. - source the following things if not done already:
export PATH="/opt/crosstool-ng/bin:/opt/qemu/bin:$PATH"
source <path-to-vivado>/Vivado/2018.3/settings64.sh
source <path-to-sdk>/SDK/2018.3/settings64.sh
source <path-to-petalinux>/petalinux-v2018.3-final/settings.sh
petalinux-util --webtalk off
- Create a file called
ZC702.spec
insidetest_repo/ZC702
and edit according to the build need. Following the file that I used for the img present in the repo:
ARCH_ZC702 = arm
BSP_ZC702 = <bsp-name>.bsp
STAGE4_PACKAGES_ZC702 = ethernet
- To build our more customised SD card image while still using the pre-built we can run
$ make BOARDDIR=test_repo PREBUILT=<recent-arm-image>.img nocheck_images