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As reported on the mailing list: https://mail.coreboot.org/hyperkitty/list/[email protected]/thread/3CC54GMEBXYVOXBJ7J5NZ5R4SQ42ZOXC/ Change-Id: I0700d3e4f684db096fea63eb9bc5add44e246758 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75604 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Stefan Reinauer <[email protected]>
The intro text is converted from wiki home page. Change-Id: I2bf0d8a3b2e16c9bb7e6fbde5931ff816aede14a Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75723 Reviewed-by: Stefan Reinauer <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Tested read/write/erase/probe operations with a ch341a_spi programmer. Datasheet is available at https://www.mouser.de/datasheet/2/590/DS-AT25DF011_032-1098683.pdf Signed-off-by: Hanno Heinrichs <[email protected]> Change-Id: I5a2141f1380e864c843d6a3008fdb02dc1b75131 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51048 Reviewed-by: Stefan Reinauer <[email protected]> Reviewed-by: Nikolai Artemiev <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
I took the original patch from Ondrej Hennel [1] and applied the requested changes. Reading, erasing and writing works. [1] https://patchwork.ozlabs.org/project/flashrom/list/?series=261647 Change-Id: Iffd7c4284d4d96b30a94f5dee882b5403fdfc183 Signed-off-by: Mario Kicherer <[email protected]> Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68295 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Nikolai Artemiev <[email protected]>
This reverts commit 0bc84bf. Change-Id: Ie538337a409f606b717d7104fad346b708f9e2f8 Signed-off-by: Arthur Heymans <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75901 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]>
Fix typo where "FEATURE_FLAGS" is spelled "FEATURE_CFLAGS", preventing the DirtyJTAG driver from being used. Signed-off-by: Jean THOMAS <[email protected]> Change-Id: I4b6bce24f34848d11731f4bc118a3052fb24e639 Reviewed-on: https://review.coreboot.org/c/flashrom/+/75891 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Peter Marheine <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]>
In ich_hwseq_get_flash_id, flash_id_to_entry would return address of a structure present in flashchips array corresponding to provided manufacture_id and model_id. If this function returns NULL and if we don't return after printing the warning using msg_pwarn, we'll be dereferencing a NULL pointer, hence the return in that if is provided. Change-Id: I35c112cd032e3b94e30c347766764392d5bbfe3d Signed-off-by: Eshan Kelkar <[email protected]> Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71872 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Nikolai Artemiev <[email protected]>
Tested: read, write and erase. Chip (and datasheet) have recenty been removed from XMC's website but can still be retrieved through web archive: https://web.archive.org/web/20221122191724/https://www.semiee.com/file/XMC/XMC-XM25QH128A.pdf Signed-off-by: Stijn Segers <[email protected]> Change-Id: Iced40403c6694a55fd648ea2785cdcba21712234 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69309 Reviewed-by: Nikolai Artemiev <[email protected]> Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]>
Change-Id: Ic5f0548f023fcd09a970148586497e00414ad1ae Signed-off-by: Joseph Goh <[email protected]> Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68278 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]>
Change-Id: I82049c6686b7199dec55082ab9cbe71bfa89d2d7 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75895 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Nikolai Artemiev <[email protected]>
This patch added support for IS25WP020, IS25WP040, and IS25WP080 SPI flash chips. The datasheet for these chips can be found at: https://www.issi.com/WW/pdf/25WP016_080_040_020.pdf Tested read, write, and erase functions on IS25WP080. Test log: Write: https://paste.flashrom.org/view.php?id=3698 Write test 2: https://paste.flashrom.org/view.php?id=3699 Erase: https://paste.flashrom.org/view.php?id=3700 Change-Id: I8a786de5cf9ffefb2d57f89bbab71e289b5c2b28 Signed-off-by: Ao Zhong <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75830 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]>
Add initial support for Macronix MX77L25650F. Can read, write and erase the chip. Change-Id: Iaea5485f8b59b8538dc47beada2c308376ea027c Signed-off-by: Artur Kowalski <[email protected]> Signed-off-by: Sergii Dmytruk <[email protected]> Signed-off-by: ServError <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68557 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]>
Change-Id: I847428535547242ff32af92c4fe8477241826814 Signed-off-by: Thomas Heijligen <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75189 Reviewed-by: Stefan Reinauer <[email protected]> Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]> Reviewed-by: Alexander Goncharov <[email protected]>
The current auto detection is kind of broken. Since the NI-845X driver package is likely not changing, hardcode `C:\Program Files (x86)\National Instuments\NI-845x\MS Visual C` as default path to search for the library and header. This can be overridden by setting `CONFIG_NI845X_LIBRARY_PATH` to the custom path. TEST=Run make HAS_LIB_NI845X=yes CONFIG_NI845X=yes successfully on MSYS2 MINGW32 Change-Id: I2115c30d0884e35eb549a31beef04d966ba4f491 Signed-off-by: Thomas Heijligen <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75234 Reviewed-by: Alexander Goncharov <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]> Reviewed-by: Stefan Reinauer <[email protected]> Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Angel Pons <[email protected]> Reviewed-by: Miklós Márton <[email protected]>
When libusb is not around for the tests struct timeval and mode_t are not defined on mingw. Add both missing header to compile the tests under MSYS2 MINGW32/64 without libusb. Change-Id: Ic76653c8f3b5d7043ab6080d4e2e1748590ad070 Signed-off-by: Thomas Heijligen <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75235 Reviewed-by: Alexander Goncharov <[email protected]> Reviewed-by: Stefan Reinauer <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
TEST=On MSYS32 MINGW32 with ni845x library installed:
meson setup -Dprogrammer=ni845x_spi build
meson compile -C build
./build/flashrom.exe lists the ni845x_spi as choice.
Without ni845x library installed but ni845x_spi disabled,
build succeeds on all platforms.
Change-Id: I2d32f11852ac1a5184af8e8683ca1914a6e72973
Signed-off-by: Thomas Heijligen <[email protected]>
Signed-off-by: Peter Marheine <[email protected]>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/75236
Reviewed-by: Anastasia Klimchuk <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>
Because this patch adds a new footprint level, Sphinx incorrectly interprets the 3 asterisks (***) as the start of a bold block, rather than a footnote marker. To work around this, use sphinx built-in footprints. Change-Id: I97ad08632f35aa241b3d19d9ce7711146e3f1f4a Signed-off-by: Thomas Heijligen <[email protected]> Signed-off-by: Peter Marheine <[email protected]> Signed-off-by: Alexander Goncharov <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75270 Reviewed-by: Anastasia Klimchuk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
This adds the current and supported system information to the error
message when an unsupported programmer is requested, making it easier
to tell what the incompatibility is.
TEST=(in mingw-ucrt64) meson setup -Dprogrammer=ni845x_spi build,
error message says the programmer needs `['windows']/['x86']` but
the system is `windows/x86_64`.
Change-Id: I6c8a8b47505f7a239160d565463ce7262fe5d5d6
Signed-off-by: Peter Marheine <[email protected]>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/75490
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Anastasia Klimchuk <[email protected]>
Change-Id: Ied858b5f1e9c4a83a6eb21dcefb288c4474b08c0 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75727 Reviewed-by: Patrick Georgi <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Datasheet: http://file2.dzsc.com/product/19/06/22/216185_132959081.pdf Tested probe, read, erase and write with CH341a. Signed-off-by: Nita Vesa <[email protected]> Change-Id: I369db9ccfd5319d28424d10f77aab49ec73a8836 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58173 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Peter Marheine <[email protected]>
Layouts can be expensive to derive (reading from flash), so we might want to reuse a layout for different purposes. Today, it's not possible to undo a flashrom_layout_include_region() operation (to, say, operate on a different region). Add such an API. Change-Id: I7ea3e0674f25e34bf2cfc8f464ae7ca1c1a3fbfd Signed-off-by: Brian Norris <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/76005 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nikolai Artemiev <[email protected]>
Instead of relying on global variables, pass and use their value or pointer to functions where possible. The usage of `io_voltage_in_mV` global var in `usb8452_spi_set_io_voltage` function is replaced with existing function argument `set_io_voltage_mV` since `set_io_voltage_mV` already contains the pointer to global var. This patch prepares the programmer to move global singleton states into a struct. TOPIC=register_master_api Change-Id: I5daeb0839a4cc18b82d38cc06eeba88a619bec61 Signed-off-by: Alexander Goncharov <[email protected]> Ticket: https://ticket.coreboot.org/issues/391 Reviewed-on: https://review.coreboot.org/c/flashrom/+/72154 Reviewed-by: Anastasia Klimchuk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
This patch prepares the programmer to move global singleton states into a struct. TOPIC=register_master_api Change-Id: Ie9620d59db229729fd8523f99b0917d938bcc4ed Signed-off-by: Alexander Goncharov <[email protected]> Ticket: https://ticket.coreboot.org/issues/391 Reviewed-on: https://review.coreboot.org/c/flashrom/+/72156 Reviewed-by: Miklós Márton <[email protected]> Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]>
Move global singleton states into a struct and store within the spi_master data field for the life-time of the driver. TOPIC=register_master_api Change-Id: I45fcb8e20582cb0c532c4a9f0c78543a25f8d484 Signed-off-by: Alexander Goncharov <[email protected]> Ticket: https://ticket.coreboot.org/issues/391 Reviewed-on: https://review.coreboot.org/c/flashrom/+/72160 Reviewed-by: Anastasia Klimchuk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Change-Id: I3118b2b036eab93e901814447543b02c760c6a80 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/76075 Reviewed-by: Nikolai Artemiev <[email protected]> Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Peter Marheine <[email protected]> Reviewed-by: Alexander Goncharov <[email protected]> Reviewed-by: Stefan Reinauer <[email protected]>
Change-Id: I7fe9ab2e27fead8e795138294219b11240f15928 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75906 Reviewed-by: Alexander Goncharov <[email protected]> Reviewed-by: Peter Marheine <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Change-Id: Ica7790667ac4c1baf961cb7a330e08178e2c0c28 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/75744 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Aarya <[email protected]>
It was not displayed, so needed to be fixed. Secondly, it is just one line and can be an inline code markup instead of a code-block (the latter was not displayed for some reasons). Change-Id: I0f26d6fb03d1491daefa4a362068f674230e94a6 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/76663 Reviewed-by: Peter Marheine <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
The link should be to another doc, that will work with any website configuration. Old link only worked for wiki. Change-Id: I6e2ec4f73494bebd5bd47bbeaa2051439d1d3bbd Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/76675 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Peter Marheine <[email protected]>
Fix broken links to dev guide and contact page Change-Id: Ide4a675049ff245e46001da1c7ef5769baf5a14e Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/76821 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
Both of these chips were tested in-circuit with an SOIC-8 clamp and two different BusPirate boards: the BPv3.6 from Adafruit (sku 237) and the BPv3.6a from Sparkfun (sku TOL-12942), on a Fedora 38 host, using flashrom 9a57031 (changes rebased since then). Change-Id: Ib3c94f03a132a912bb4bb9d36e8783f4468587c4 Signed-off-by: Samantaz Fox <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83970 Reviewed-by: Anastasia Klimchuk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
removed FEATURE_WRSR_EXT2 from the model after datasheet review. replace printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, .unlock = SPI_DISABLE_BLOCKPROTECT, with .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, GD25B256E: 3V 256Mbit, Quad enabled. GD25R256E: GD25B256E features + RPMC, so they share the same datasheet on flash side https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00658-GD25B256E-Rev1.1.pdf Tested both models on ch347 with erase, write, read and protection. Change-Id: Ie733e0c2e35fa4797f5198f2c8334469b65f402c Signed-off-by: Victor Lim <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83998 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]>
CH347 SPI interface supports up to 60M. For example, to set a 30M spi rate, use -p ch347_spi:spispeed=30M. Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Signed-off-by: ZhiYuanNJ Liu <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82776 Reviewed-by: Nicholas Chin <[email protected]> Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]>
GD25B512MF: 3V 512Mbit, QE = 1 GD25R512MF: GD25B512MF feature + RPMC These two part share the same datasheet on the flash side. https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20240412/DS-00975-GD25B512MF-Rev1.1.pdf Tested both models on ch347 with erase, write, read, and protection. Change-Id: I9821efb34fb4abb806ad52acec46aad186888c07 Signed-off-by: Victor Lim <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84083 Reviewed-by: Anastasia Klimchuk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
This makes flashrom sleep more eagerly rather than busy-waiting, observing that most delays in flashrom are either less than 100 microseconds (barely enough time to get any work done, even on a fast machine) or much more than 1 millisecond (very wasteful to busy-loop). Since we believe most systems offer good timer resolution that should provide sleep latency on the order of 100 microseconds, this is a reasonable default. For DOS, the default is set to 50ms because the best available timing source on DOS only ticks at about 20 Hz. Signed-off-by: Peter Marheine <[email protected]> Change-Id: I0f431d240c670446218b14811ef62a34e4c83da2 Reviewed-on: https://review.coreboot.org/c/flashrom/+/81608 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]>
The patch adds new functionality to the test: tracking the areas of chip memory that were modified (i.e. by erase or write operation), and then checking those areas were completely covered by verify operation. The test operates over the mock chip memory of 16 bytes, so it is possible to track each byte which was modified, and assert that is has been verified afterwards. Adding the test found a bug which is fixed in this commit: Post-cleanup after processing unaligned region for the case when end region needs to be extended to align with erase block. Writing was done correctly, but post-processing of newcontents could cause one-off offset at the end of the region, which would make verification appear false-negative (see test cases #16-19). Change-Id: I3c5d55a0deb20f23f4072caac8c0dce04cc98fd4 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84078 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Peter Marheine <[email protected]>
Based on public Intel 700 Series PCH datasheet, DOC 743835 rev 004. The IDs of IoT chipset SKUs (ending with E) can only be found in "12th Gen Intel® Core™ Processors Family (Formerly Known as Alder Lake -S) for IoT Platforms External Design Specification (EDS) Addendum" DOC 634528 rev 2.7 (NDA). TEST=Probe flash on Z790 chipset. Run the ich_descriptors_tool and check the output is correct as expected. Change-Id: I13ac52d5400c0e2260e12d605077fc2182c379ef Signed-off-by: Michał Żygowski <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83854 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]> Reviewed-by: Sergii Dmytruk <[email protected]>
Fix a segmentation fault that is caused by accessing an invalid "subedata" pointer on the last iteration of the init_eraseblock loop. Instead, short circuit the loop condition to check the sub block index first, and do not access the invalid pointer if it is the last sub block. Issue was encountered in: - OS: OpenBSD 7.5 amd64 - Compiler: clang 16.0.6 - Chip: Macronix MX25U6435E/F BUG=https://ticket.coreboot.org/issues/555 Change-Id: I61bf0d93aa9f0b2b420b146be16fcd5124f0dc5d Signed-off-by: Grant Pannell <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84234 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: DigitalDJ Reviewed-by: Anastasia Klimchuk <[email protected]>
New check was added to `check_block_eraser` in commit 0f389ae but it was not handling FEATURE_NO_ERASE chips. This patch fixes processing such chips and adds test to run write and verify with dummyflasher for FEATURE_NO_ERASE chips. Ticket: https://ticket.coreboot.org/issues/553 Change-Id: I582fe00da0715e9b5e92fcc9d15d5a90a2615117 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84203 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Peter Marheine <[email protected]>
Co-developed-by: Anastasia Klimchuk <[email protected]> Co-developed-by: Sergii Dmytruk <[email protected]> Change-Id: I1ad7f89b0a6c91907440e3897ac262bd82f846d5 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84421 Reviewed-by: Sergii Dmytruk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Co-developed-by: Anastasia Klimchuk <[email protected]> Co-developed-by: Sergii Dmytruk <[email protected]> Change-Id: I104611d42b301662e2c833498aca99c879685846 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84422 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Sergii Dmytruk <[email protected]>
The patch adds a section on a manpage to explain the freq parameter in dummyflasher, and tests for various valid and invalid values of freq parameter. Co-developed-by: Anastasia Klimchuk <[email protected]> Co-developed-by: Sergii Dmytruk <[email protected]> Change-Id: Iaca5d95f8f977bf0c2283c6458d8977e6ce70251 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84423 Reviewed-by: Sergii Dmytruk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
The existing page on old wiki is very small and fits into a manpage item: https://wiki.flashrom.org/NICIntel Change-Id: I139065611c68c0fa0a675fe49a6f8bc20e9057f7 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83751 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Stefan Reinauer <[email protected]>
From page: https://wiki.flashrom.org/FT2232SPI_Programmer The sections about openbiosprog-spi, RushSPI, Amontec have broken links and are not added to this patch. If we find out where these project live now (if they still are active), would be good to add the info later. Change-Id: Id30b6c92838d7ca6e26a4cc3e0aeeb3f3ce07668 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83866 Reviewed-by: Stefan Reinauer <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Without the header being explicitly included, scan-build run on CI was returning errors for these files, such as: include the header <stdlib.h> or explicitly provide a declaration for 'calloc' The functions in question were calloc, free, etc. Change-Id: I4b79c5f86c074c456533296c309293e4064abe3f Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84455 Reviewed-by: Stefan Reinauer <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
meson's default behavior is to install subprojects, so because we use a wrap to get cmocka if needed and the cmocka wrap sets install=true unless cross-compiling, cmocka headers and libraries will be installed by `meson install`. This isn't useful (because cmocka is used only for tests which don't get installed), and can cause install errors in some configurations. meson can be told to never install subprojects with `meson install --skip-subprojects` which solves this, but is inconvenient because that option must be specified on the command line and there is little hope of meson's default behavior changing [1]. To fix this, I've replaced `patch_url` for the wrap with an included `patch_directory` instead, which was created by unpacking the original archive pointed to by `patch_url` and setting `install : false` in src/meson.build. A more concise option to make the same change would be to make the change to the `install` option in a new patch specified via `diff_files` (which works because patches from `diff_files` are applied after applying the `patch_*` archive), but `diff_files` is not supported by Meson before version 0.63.0 which would require increasing flashrom's minimum meson version from the current 0.56.0. This seems too new, since meson 0.56 was released in October 2020 while meson 0.63 was released in July 2022. [1]: mesonbuild/meson#10561 (comment) BUG=https://ticket.coreboot.org/issues/561 Change-Id: I15f549175e2d5d52979814d7f7530da868871ce8 Signed-off-by: Peter Marheine <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84557 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]>
The function for reprogramming on the fly was using the default configuration O_ST_M25P as a base and the position 2 as the position to reprogram. Position 2 corresponds to JEDEC_SE which is often useful for chip erase (when less than whole chip needs to be erased). This patch changes the default position to reprogram to 4, which corresponds to JEDEC_REMS. It is used less often, but if it needs to be used, it will be discovered missing and reprogrammed back. For erase opcodes, there is usually several of them available. So if one is missing, erase still can be performed with the remaining ones. However, this hides the fact that one of available erase opcodes is missing (it won't be reprogrammed back), and also it gives non-optimal erase layout. Context: https://ticket.coreboot.org/issues/556 Change-Id: I6bc855daedf0af2e8de191f23a3512de3ebc3fef Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84567 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Nikolai Artemiev <[email protected]>
POSSIBLE_OPCODES[] is never modified, so mark it as read-only. Change-Id: I217f8a9e50b9e2e9f2731adec89a46780874c754 Signed-off-by: persmule <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84595 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]> Reviewed-by: Nikolai Artemiev <[email protected]>
There seems no problem to use ich_spi_probe_opcode() for spi_master::probe_opcode() on ich7, so we may merge former spi_master_ich7 and spi_master_ich9 into spi_master_ich, for both init_ich7_spi() and init_ich_default(). Change-Id: I6a65c97e910622a55da7cef8a10de3af6a99c9e8 Signed-off-by: persmule <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84593 Reviewed-by: Anastasia Klimchuk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Nikolai Artemiev <[email protected]>
ich_spi_send_command() and ich_spi_send_multicommand() will overwrite the "Sector erase" opcode with the opcode for command via reprogram_opcode_on_the_fly(), but not restore it, causing the "Sector erase" opcode may get lost after sending commands, leaving only "Bulk erase" opcode which erase the whole chip available. In the mean time, ich_spi_probe_opcode() used not to report opcodes in POSSIBLE_OPCODES[] but not in curopcodes->opcode[] as supported. Now, if the opcode being probed is not in curopcodes->opcode[] but in POSSIBLE_OPCODES[], it will be reported as supported, and programmed later by ich_spi_send_(multi)command(). Fix:https://ticket.coreboot.org/issues/556 Change-Id: I3fc831fc072e2af9265835cb2f71bf8c222c6a64 Signed-off-by: persmule <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84253 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]> Reviewed-by: Nikolai Artemiev <[email protected]>
Change-Id: Ic808508b5da431d6c0b88a9b2847c34c7b02cfe0 Signed-off-by: Anastasia Klimchuk <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84679 Reviewed-by: Stefan Reinauer <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
A larger (not the smallest) erase block used to get erased when half of sub-blocks it contains need erase, which has at least 2 issues: 1. The rest half of sub-blocks that do not need erase are also erased, introducing some erase overheads. 2. More severely, since this logic only selects a block and delects its sub-blocks when half of sub-blocks need erase, but this logic does not deselect "nested sub-blocks (sub-blocks of sub-block)" not reach the limit under this block, the logic may cause duplicated erase. For example, if a erase block (often the largest one corresponding to the whole chip) has half of its sub-blocks and some incontiguous nested sub-blocks needing erase, these double sub-blocks will end up being erased twice, introducing even more erase overheads than whole-chip erase. The older behavior of flashrom before adding erasure_layout.c, when no communicational error occurs, will neither erase blocks that do not need erase, nor cause duplicated erase. Higher efficiency should be achieved without introducing extra erase overheads, by allowing combining contiguous small erase blocks only when they can coincidently form a larger erase block. Change-Id: I9e10749186e395da67ec80e296119f33c3f83122 Signed-off-by: persmule <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84614 Reviewed-by: Peter Marheine <[email protected]> Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Anastasia Klimchuk <[email protected]>
GD25F64F: 3V 64Mbit, high performance Tested on ch347 with erase, write, read, and protection Change-Id: I07005f1589b76c8a61a1a744b16dc6b0c9020e11 Signed-off-by: Victor Lim <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84705 Reviewed-by: Anastasia Klimchuk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
GD25F256F: 3V 256Mbit, high performance Tested on ch347 with erase, write, read, and protection Change-Id: Ibbbbb8a55adbcbc2ee1785782c4eb3771d50c167 Signed-off-by: Victor Lim <[email protected]> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84090 Reviewed-by: Anastasia Klimchuk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Change-Id: I5fa58b9dbafced0587c881357c79ab716d8a178d Signed-off-by: Pawel Langowski <[email protected]>
Change-Id: I62a9fffee53a38e020689dc47a4ecfd9724e0647 Signed-off-by: Pawel Langowski <[email protected]>
Change-Id: I4ca1ec3b573443273f6dfd87c58a18ebe16b69b1 Signed-off-by: Pawel Langowski <[email protected]>
Change-Id: I3d947904ad3dfc42e47f1019702dc4dd05fb91cc Signed-off-by: Pawel Langowski <[email protected]>
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