All Intel SOCs use input pullup 20K as not connected GPIO.
Also GPIO output mode may be harmful.

Signed-off-by: Michał Żygowski <[email protected]>

Fixes a problem where changing ME binary in the config would not result
in the desired ME binary be included in the rebuilt coreboot binary.

Signed-off-by: Michał Żygowski <[email protected]>

…d an error in log

Signed-off-by: Michał Żygowski <[email protected]>

BayTrail EDS is correct. MIPI is disabled in a different manner which
does not use FUNC_DIS register.

Signed-off-by: Michał Żygowski <[email protected]>

Even if PCIEXP_ASPM is not selected, it doesn't mean all PCIe
devices will have the correct ASPM disabled state set. Ensure
the ASPM is disabled if it is not selected.

Signed-off-by: Michał Żygowski <[email protected]>

Leave the choice to enable ASPM to the user via Kconfig.

Signed-off-by: Michał Żygowski <[email protected]>

Native code misses the interrupt configuration for LPSS devices.
Replicate the FSP default interrupt configuration.

Signed-off-by: Michał Żygowski <[email protected]>

…erly

Disable OTG and MIPI as described in BayTrail BWG Vol. 2
(Document Number: 514148, Rev, 1.47).

Signed-off-by: Michał Żygowski <[email protected]>

By default FSP was configuring the ports as hotpluggable.
Allow hotplug configuration based on Kconfig. Use the
procedure described in Bay Trail BWG Vol.2 (Document
Number: 514148, Rev, 1.47) to initialize PCIe port.

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Minnowboard has two SATA ports: one on the standard SATA connector,
second on the expansion I/O header.

Signed-off-by: Michał Żygowski <[email protected]>

Describe OTG controller in the devicetree. Also add comment about
known issue with writing to OTG IOSF port that will cause a hang
if OTG is disabled runtime using PMC FUNC_DIS. When OTG is disabled
by a soft strap in the flash descriptor, the issue does not occur
though.

Signed-off-by: Michał Żygowski <[email protected]>

…s per BWG

Implement additional LPSS programming requirements per Bay Trail BWG
Vol.2 (Document Number 514148, Rev, 1.47). These settings also reflect
the the FSP behavior.

Signed-off-by: Michał Żygowski <[email protected]>

LPC bridge device must call enable_resources to recursively enable
resources for child devices. Otherwise child devices behind LPC bus
may have misconfigured resources.

Signed-off-by: Michał Żygowski <[email protected]>

…obing

After VGA16 bit was probed, it was never clear resulting in VGA16 bit
being enabled in all ports without any VGA device behind them. Clear
the VGA16 bit after probing and let coreboot set it back later for
devices where it is necessary.

Signed-off-by: Michał Żygowski <[email protected]>

Implement TXE BIOS flow as per Bay Trail TXE BWG
(Document Number: 514966, Revision 0.7).

Signed-off-by: Michał Żygowski <[email protected]>

If the CBFS end is not at address 0xFFFFFFFF, then SeabIOS will not
be able to find CBFS. This option allows to set the CBFS end in
situations where COREBOOT region does not end at address 0xFFFFFFFF.

Signed-off-by: Michał Żygowski <[email protected]>

With CBFS_VERIFICATION one cannot fetch the early microcode update
from CBFS, as walkcbfs_asm is unsafe to be compiled with
CBFS_VERIFICATION. As a workaround, put a microcode copy in the IBB
under a fixed address. Bootblock and microcode will be verified by
TXE when TXE_SECURE_BOOT is enabled, so it will be safe to use.

Also put the microcode and bootblock in the BOOTBLOCK region which
will cover whole IBB to cleanly separate code and data to be verfied
by TXE from the rest of CBFS. it will make the updates easier and
keep CBFS_VERIFICATION working properly.

Signed-off-by: Michał Żygowski <[email protected]>

The spd_add_smbios17 function already assumes MEMORY_BUS_WIDTH_64
non-ECC only, but did not fill in the ecc_type information, which
resulted in SMBIOS type 16 Memory Error Correction field to be out
of specitions (0 is not defined). Fill in the ecc_type field
as MEMORY_ARRAY_ECC_NONE.

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Intel Bay Trail SoCs (confirmed on Atom E3845) have leading spaces
in the CPU brand string returned by CPUID. Strip these spaces so
that SMBIOS CPU string does not look weird in the EDK2 setup page
and the dmidecode output.

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>

Signed-off-by: Filip Lewiński <[email protected]>

…f hotplug

Signed-off-by: Filip Lewiński <[email protected]>

Signed-off-by: Filip Lewiński <[email protected]>

Required for proper BIOS lock functionality, implements
mainboard_get_spi_config

Signed-off-by: Filip Lewiński <[email protected]>

Signed-off-by: Filip Lewiński <[email protected]>

Signed-off-by: Filip Lewiński <[email protected]>

Signed-off-by: Filip Lewiński <[email protected]>

This reverts commit dd311d8.

WIP

Signed-off-by: Filip Lewiński <[email protected]>

Signed-off-by: Michał Żygowski <[email protected]>