Protectli fw6 support

.github/workflows/build.yml

@@ -75,7 +75,7 @@ jobs:
     strategy:
       matrix:
         vendor: [ protectli ]
-        model: [ vp46xx, V1210, V1410, V1610 ]
+        model: [ vp46xx, V1210, V1410, V1610, FW6 ]
     steps:
       - name: Checkout repository
         uses: actions/checkout@v3

build.sh

@@ -160,6 +160,47 @@ function build_v1x10 {
 	fi
 }
 
+function build_fw6 {
+	DEFCONFIG="configs/config.protectli_fw6"
+	FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"')
+
+	if [ ! -d 3rdparty/blobs/mainboard ]; then
+		git submodule update --init --checkout
+	fi
+
+	if [ ! -d 3rdparty/blobs/mainboard/protectli/vault_kbl ]; then
+		if [ -f protectli_blobs.zip ]; then
+			unzip protectli_blobs.zip -d 3rdparty/blobs/mainboard
+		else
+			echo "Platform blobs missing! You must obtain them first."
+			exit 1
+		fi
+	fi
+
+	docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \
+		-v $HOME/.ssh:/home/coreboot/.ssh \
+		-w /home/coreboot/coreboot coreboot/coreboot-sdk:2021-09-23_b0d87f753c \
+		/bin/bash -c "make distclean"
+
+	cp $DEFCONFIG .config
+
+	echo "Building Dasharo for Protectli FW6 (version $FW_VERSION)"
+
+	docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \
+		-v $HOME/.ssh:/home/coreboot/.ssh \
+		-w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \
+		/bin/bash -c "make olddefconfig && make -j$(nproc)"
+
+	cp build/coreboot.rom protectli_fw6_${FW_VERSION}.rom
+	if [ $? -eq 0 ]; then
+		echo "Result binary placed in $PWD/protectli_fw6_${FW_VERSION}.rom"
+		sha256sum protectli_fw6_${FW_VERSION}.rom > protectli_fw6_${FW_VERSION}.rom.sha256
+	else
+		echo "Build failed!"
+		exit 1
+	fi
+}
+
 
 CMD="$1"
 
@@ -192,6 +233,9 @@ case "$CMD" in
     "v1610" | "V1610" )
         build_v1x10 "v1610"
         ;;
+    "fw6" | "FW6" )
+        build_fw6
+        ;;
     *)
         echo "Invalid command: \"$CMD\""
         usage

configs/config.protectli_fw6

@@ -0,0 +1,46 @@
+CONFIG_LOCALVERSION="v1.1.0"
+CONFIG_OPTION_BACKEND_NONE=y
+CONFIG_VENDOR_PROTECTLI=y
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000
+CONFIG_EDK2_BOOT_TIMEOUT=6
+CONFIG_USE_LEGACY_8254_TIMER=y
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_BOARD_PROTECTLI_FW6=y
+CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR)/bootsplash.bmp"
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_RUN_FSP_GOP=y
+CONFIG_DRIVERS_EFI_VARIABLE_STORE=y
+CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y
+CONFIG_DRIVERS_GENERIC_CBFS_UUID=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set
+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set
+CONFIG_POST_DEVICE_LPC=y
+CONFIG_PAYLOAD_EDK2=y
+CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2"
+CONFIG_EDK2_TAG_OR_REV="1174634037dc986a2221176657407ea3447cf6a6"
+CONFIG_EDK2_USE_EDK2_PLATFORMS=y
+CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms"
+CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf"
+CONFIG_EDK2_CBMEM_LOGGING=y
+CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
+# CONFIG_EDK2_PS2_SUPPORT is not set
+CONFIG_EDK2_SERIAL_SUPPORT=y
+CONFIG_EDK2_ENABLE_IPXE=y
+CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities"
+CONFIG_EDK2_SECURE_BOOT=y
+# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set
+CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y
+CONFIG_EDK2_INTEL_ME_DISABLED_HECI=y
+CONFIG_EDK2_DASHARO_USB_CONFIG=y
+CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y
+CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y
+CONFIG_EDK2_BOOT_MENU_KEY=0x0015
+CONFIG_EDK2_SETUP_MENU_KEY=0x0008
+CONFIG_EDK2_DISABLE_OPTION_ROMS=y
+CONFIG_PXE_ADD_SCRIPT=y
+CONFIG_PXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe"
+CONFIG_PXE_CUSTOM_BUILD_ID="0123456789"

payloads/external/edk2/Makefile

@@ -404,7 +404,7 @@ print:
 	echo "   Repository:     $(CONFIG_EDK2_REPOSITORY)"
 	echo "   Branch:         $(CONFIG_EDK2_TAG_OR_REV)"
 	echo "   Packages path:  $(PACKAGES_PATH)"
-	echo " $(BUILD_STR)" | \
+	echo " -a IA32 -a X64 -b $(RELEASE_STR) $(BUILD_STR)" | \
 		sed -e 's/--/-/g' -e 's/-/\n   /g' | sort | sed \
 		-e 's/a /Architecture:   /g' \
 		-e 's/b /Release:        /g' \

src/include/device/pci_ids.h

@@ -4377,6 +4377,8 @@
 #define PCI_DID_INTEL_GLK_CSE0			0x319a
 #define PCI_DID_INTEL_CNL_CSE0			0x9de0
 #define PCI_DID_INTEL_SKL_CSE0			0x9d3a
+#define PCI_DID_INTEL_SKL_H_CSE0		0xa13a
+#define PCI_DID_INTEL_KBL_H_CSE0		0xa2ba
 #define PCI_DID_INTEL_LWB_CSE0			0xa1ba
 #define PCI_DID_INTEL_LWB_CSE1			0xa1bb
 #define PCI_DID_INTEL_LWB_CSE2			0xa1be

src/mainboard/protectli/vault_kbl/Kconfig

@@ -9,8 +9,9 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_LIBGFXINIT
 	select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
 	select SOC_INTEL_KABYLAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPI_FLASH_MACRONIX
-	select SUPERIO_ITE_IT8772F
+	select SUPERIO_ITE_IT8613E
 	select CRB_TPM
 	select HAVE_INTEL_PTT
 	select MAINBOARD_HAS_TPM2
@@ -19,7 +20,10 @@ config MAINBOARD_DIR
 	default "protectli/vault_kbl"
 
 config MAINBOARD_PART_NUMBER
-	default "FW6"
+	default	"FW6"
+
+config MAINBOARD_FAMILY
+	default "Vault"
 
 config DIMM_MAX
 	default 2
@@ -28,21 +32,33 @@ config DIMM_SPD_SIZE
 	default 512
 
 config MAX_CPUS
-	int
-	default 4
+	default 8
+
+config DEVICETREE
+	default "devicetree.cb"
 
 config VGA_BIOS_ID
-	string
-	default "8086,5916" # 8086,5906 for FW6A
+	default "8086,5916" # FW6A/B/C
+
+config VGA_BIOS_SECOND_ID
+	default "8086,5917" # FW6D/E
 
 config PXE_ROM_ID
-	string
 	default "8086,150c"
 
 config CBFS_SIZE
 	default 0x600000
 
-config USE_PM_ACPI_TIMER
-	default n
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config BEEP_ON_BOOT
+	bool "Beep on successful boot"
+	default y
+	help
+	  Make the platform beep using the PC speaker in final coreboot phase.
+	  May serve as a useful indicator in headless mode that platform is
+	  properly booting.
+
 
 endif

src/mainboard/protectli/vault_kbl/Makefile.inc

@@ -2,6 +2,9 @@
 
 bootblock-y += bootblock.c
 
-ramstage-y += ramstage.c
-
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+
+bootblock-y += die.c
+romstage-y += die.c
+ramstage-y += die.c
+smm-y += die.c

src/mainboard/protectli/vault_kbl/acpi/ec.asl

@@ -1,3 +1 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
+/* SPDX-License-Identifier: GPL-2.0-or-later */

src/mainboard/protectli/vault_kbl/acpi/superio.asl

@@ -1,3 +1,7 @@
-/* SPDX-License-Identifier: CC-PDDC */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
 
-/* Please update the license if adding licensable material. */
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+#define IT8786E_SHOW_UARTA
+
+#include <superio/ite/it8613e/acpi/superio.asl>

src/mainboard/protectli/vault_kbl/board.fmd

@@ -0,0 +1,14 @@
+FLASH@0xff800000 8M {
+	SI_ALL 2M {
+		SI_DESC 4K
+		SI_ME
+	}
+
+	SMMSTORE(PRESERVE) 256K
+	RW_MRC_CACHE 64K
+	BOOTSPLASH(CBFS) 512K
+	WP_RO {
+		FMAP 0x800
+		COREBOOT(CBFS)
+	}
+}

src/mainboard/protectli/vault_kbl/board_info.txt

@@ -1,5 +1,5 @@
 Vendor name: Protectli
-Board name: FW6A/FW6B/FW6C
+Board name: FW6A/FW6B/FW6C/FW6D/FW6E
 Category: sbc
 ROM protocol: SPI
 ROM socketed: n

src/mainboard/protectli/vault_kbl/bootblock.c

@@ -1,15 +1,33 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <bootblock_common.h>
-#include <superio/ite/it8772f/it8772f.h>
+#include <device/pnp_ops.h>
 #include <superio/ite/common/ite.h>
+#include <superio/ite/it8613e/it8613e.h>
 
-#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
-#define UART_DEV PNP_DEV(0x2e, IT8772F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO)
+#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1)
+
+/* Return an id of the installed chip. */
+static uint16_t ite_read_id(void)
+{
+	pnp_enter_conf_state(GPIO_DEV);
+	uint16_t id = (pnp_read_config(GPIO_DEV, 0x20) << 8)
+		| pnp_read_config(GPIO_DEV, 0x21);
+	pnp_exit_conf_state(GPIO_DEV);
+	return id;
+}
 
 void bootblock_mainboard_early_init(void)
 {
-	ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24);
+	if (ite_read_id() == 0x8613){
+		ite_reg_write(GPIO_DEV, 0x23, 0x49); /* CLK Select Ext CLKIN, 24MHz */
+		ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* Disable k8 power seq */
+		ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */
+		ite_reg_write(GPIO_DEV, 0x71, 0x08); /* Ext CLKIN PCICLK */
+	} else {
+		ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24);
+	}
 	ite_enable_3vsbsw(GPIO_DEV);
 	ite_kill_watchdog(GPIO_DEV);
 	ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);