mb/clevo/mtl-h: enable LPSS UART for debug console

Signed-off-by: Michał Kopeć <[email protected]>
Dasharo · Nov 18, 2024 · db1d9cd · db1d9cd
1 parent 21d42ff
commit db1d9cd
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Showing 7 changed files with 22 additions and 4 deletions.
diff --git a/src/mainboard/clevo/mtl-h/Kconfig b/src/mainboard/clevo/mtl-h/Kconfig
@@ -13,6 +13,7 @@ config BOARD_CLEVO_MTLH_COMMON
 	select HAVE_CMOS_DEFAULT
 	select HAVE_OPTION_TABLE
 	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select NO_UART_ON_SUPERIO

diff --git a/src/mainboard/clevo/mtl-h/Makefile.inc b/src/mainboard/clevo/mtl-h/Makefile.inc
@@ -3,6 +3,7 @@
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
 bootblock-y += bootblock.c
+bootblock-y += gpio_early.c
 
 romstage-y += romstage.c
 romstage-y += variants/$(VARIANT_DIR)/gpio.c

diff --git a/src/mainboard/clevo/mtl-h/bootblock.c b/src/mainboard/clevo/mtl-h/bootblock.c
@@ -5,4 +5,5 @@
 
 void bootblock_mainboard_early_init(void)
 {
+	mainboard_configure_early_gpios();
 }
diff --git a/src/mainboard/clevo/mtl-h/gpio_early.c b/src/mainboard/clevo/mtl-h/gpio_early.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/clevo/mtl-h/include/mainboard/gpio.h b/src/mainboard/clevo/mtl-h/include/mainboard/gpio.h
@@ -11,6 +11,7 @@
 		PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
 #endif
 
+void mainboard_configure_early_gpios(void);
 void mainboard_configure_gpios(void);
 
 #endif
diff --git a/src/mainboard/clevo/mtl-h/variants/dgpu/gpio.c b/src/mainboard/clevo/mtl-h/variants/dgpu/gpio.c
@@ -130,8 +130,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2),	/* CNV_MFUART2_TXD */
 	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),	/* I2C3_SDA */
 	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),	/* I2C3_SCL */
-	PAD_CFG_GPO(GPP_H08, 0, DEEP),	/* GPIO */
-	PAD_CFG_GPO(GPP_H09, 0, DEEP),	/* GPIO */
+	//PAD_CFG_GPO(GPP_H08, 0, DEEP),	/* GPIO */
+	//PAD_CFG_GPO(GPP_H09, 0, DEEP),	/* GPIO */
 	PAD_CFG_GPO(GPP_H10, 0, DEEP),	/* GPIO */
 	PAD_CFG_GPO(GPP_H11, 0, DEEP),	/* GPIO */
 	PAD_CFG_GPO(GPP_H12, 0, DEEP),	/* GPIO */

diff --git a/src/mainboard/clevo/mtl-h/variants/igpu/gpio.c b/src/mainboard/clevo/mtl-h/variants/igpu/gpio.c
@@ -544,11 +544,11 @@ static const struct pad_config gpio_table[] = {
 
 	/* GPP_H08 - GPIO */
 	/* DW0: 0x44000200, DW1: 0x00000000 */
-	PAD_CFG_GPO(GPP_H08, 0, DEEP),
+	//PAD_CFG_GPO(GPP_H08, 0, DEEP),
 
 	/* GPP_H09 - GPIO */
 	/* DW0: 0x44000200, DW1: 0x00000000 */
-	PAD_CFG_GPO(GPP_H09, 0, DEEP),
+	//PAD_CFG_GPO(GPP_H09, 0, DEEP),
 
 	/* GPP_H10 - GPIO */
 	/* DW0: 0x44000200, DW1: 0x00000000 */