mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb: disable

ASPM for LAN controllers Signed-off-by: Filip Lewiński <[email protected]>
Dasharo · Nov 5, 2024 · 75aba1b · 75aba1b
1 parent 7161caa
commit 75aba1b
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Showing 4 changed files with 20 additions and 8 deletions.
diff --git a/configs/config.protectli_vp2430 b/configs/config.protectli_vp2430
@@ -1,23 +1,23 @@
-CONFIG_LOCALVERSION="v0.9.0-rc1_serial2"
-CONFIG_BOARD_PROTECTLI_VP2430=y
+CONFIG_LOCALVERSION="v0.9.0-rc1"
 CONFIG_VENDOR_PROTECTLI=y
 CONFIG_VBOOT=y
 CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin"
 CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin"
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000
 CONFIG_EDK2_BOOT_TIMEOUT=6
 CONFIG_HAVE_IFD_BIN=y
+CONFIG_BOARD_PROTECTLI_VP2430=y
 CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp"
 CONFIG_TPM_MEASURED_BOOT=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_INTEL_ME_DISABLED_HECI=y
+CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y
 CONFIG_DRIVERS_EFI_VARIABLE_STORE=y
 CONFIG_TPM2=y
 CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y
 CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y
 CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y
 CONFIG_BOOTMEDIA_SMM_BWP=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
 CONFIG_PAYLOAD_EDK2=y
 CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2"
 CONFIG_EDK2_TAG_OR_REV="e91a6e499eff7ff601fe65383d16811ee96fce2c"

diff --git a/src/mainboard/protectli/vault_adl_n/mainboard.c b/src/mainboard/protectli/vault_adl_n/mainboard.c
@@ -11,6 +11,10 @@
 
 const char *smbios_mainboard_product_name(void)
 {
+	if (CONFIG(BOARD_PROTECTLI_VP2430)){
+		return "VP2430";
+	}
+
 	u32 tmp[13];
 	const char *str = "Unknown Processor Name";
 

diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp2430/gpio.c b/src/mainboard/protectli/vault_adl_n/variants/vp2430/gpio.c
@@ -574,7 +574,7 @@ static const struct pad_config gpio_table[] = {
 	/* DW0: 0x44000702, DW1: 0x00000000 */
 	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */
 	/* PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), */
-	_PAD_CFG_STRUCT(GPP_H19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 
 	/* GPP_H20 - GPIO */
 	/* DW0: 0x44000300, DW1: 0x00000000 */
@@ -618,25 +618,25 @@ static const struct pad_config gpio_table[] = {
 	/* DW0: 0x44000700, DW1: 0x00000000 */
 	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
 	/* PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), */
-	_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 
 	/* GPP_D6 - SRCCLKREQ1# */
 	/* DW0: 0x44000700, DW1: 0x00000000 */
 	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
 	/* PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), */
-	_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
 
 	/* GPP_D7 - SRCCLKREQ2# */
 	/* DW0: 0x44000700, DW1: 0x00000000 */
 	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
 	/* PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), */
-	_PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 
 	/* GPP_D8 - SRCCLKREQ3# */
 	/* DW0: 0x44000700, DW1: 0x00000000 */
 	/* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */
 	/* PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), */
-	_PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
 
 	/* GPP_D9 - BSSB_LS2_RX */
 	/* DW0: 0x44001700, DW1: 0x00003c00 */

diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb b/src/mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb
@@ -27,6 +27,8 @@ chip soc/intel/alderlake
 		device ref pcie_rp2 on
 			register "pch_pcie_rp[PCH_RP(2)]" = "{
 				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,
+				.pcie_rp_aspm = ASPM_DISABLE,
+				.PcieRpL1Substates = L1_SS_DISABLED,
 				.clk_src = 0,
 				.clk_req = 0,
 			}"
@@ -35,6 +37,8 @@ chip soc/intel/alderlake
 		device ref pcie_rp3 on
 			register "pch_pcie_rp[PCH_RP(3)]" = "{
 				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,
+				.pcie_rp_aspm = ASPM_DISABLE,
+				.PcieRpL1Substates = L1_SS_DISABLED,
 				.clk_src = 1,
 				.clk_req = 1,
 			}"
@@ -43,6 +47,8 @@ chip soc/intel/alderlake
 		device ref pcie_rp4 on
 			register "pch_pcie_rp[PCH_RP(4)]" = "{
 				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,
+				.pcie_rp_aspm = ASPM_DISABLE,
+				.PcieRpL1Substates = L1_SS_DISABLED,
 				.clk_src = 2,
 				.clk_req = 2,
 			}"
@@ -51,6 +57,8 @@ chip soc/intel/alderlake
 		device ref pcie_rp7 on
 			register "pch_pcie_rp[PCH_RP(7)]" = "{
 				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,
+				.pcie_rp_aspm = ASPM_DISABLE,
+				.PcieRpL1Substates = L1_SS_DISABLED,
 				.clk_src = 3,
 				.clk_req = 3,
 			}"