src/southbridge/intel/common/spi.c: add SMIWPEN for BYT platforms

Signed-off-by: Filip Lewiński <[email protected]>
Dasharo · Sep 9, 2024 · 2468b93 · 2468b93
1 parent 56c4b20
commit 2468b93
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Showing 4 changed files with 58 additions and 3 deletions.
diff --git a/src/soc/intel/baytrail/include/soc/spi.h b/src/soc/intel/baytrail/include/soc/spi.h
@@ -24,6 +24,10 @@
 #define UVSCC				0xc8
 #define SCS				0xf8
 # define SMIWPEN			(0x1 << 7)
+# define SMIWPST			(0x1 << 6)
+#define BCS				0x6c
+# define BCS_SMIWPST		(0x1 << 0)
+# define BCS_SMIWPEN		(0x1 << 1)
 #define BCR				0xfc
 # define EISS				(0x1 << 5)
 # define SRC_MASK			(0x3 << 2)

diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
@@ -394,6 +394,8 @@ void southbridge_smi_handler(void)
 			continue;
 
 		if (southbridge_smi[i] != NULL) {
+			printk(BIOS_DEBUG,
+					"SMI_STS[%d] occurred, calling corresponding handler\n", i);
 			southbridge_smi[i]();
 		} else {
 			printk(BIOS_DEBUG,

diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
@@ -28,6 +28,7 @@
 #include <soc/spi.h>
 #include "chip.h"
 #include <acpi/acpigen.h>
+#include <southbridge/intel/common/spi.h>
 
 static void sc_add_mmio_resources(struct device *dev)
 {
@@ -786,6 +787,7 @@ static void finalize_chipset(void *unused)
 	/*  Set the CF9 lock */
 	write32(etr, read32(etr) | CF9LOCK);
 
+	spi_finalize_ops();
 	if (mainboard_get_spi_config(&cfg) < 0) {
 		printk(BIOS_DEBUG, "No SPI lockdown configuration.\n");
 	} else {

diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
@@ -1110,29 +1110,76 @@ __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_co
 {
 }
 
+#if CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
+#define ILB_BASE_ADDRESS		0xfed08000
+#define SPI_BASE_ADDRESS		0xfed01000
+#define SCS				0xf8
+# define SMIWPEN			(0x1 << 7)
+# define SMIWPST			(0x1 << 6)
+
+#define BCS				0x6c
+# define BCS_SMIWPST		(0x1 << 0)
+# define BCS_SMIWPEN		(0x1 << 1)
+
+#define BCR				0xfc
+# define EISS				(0x1 << 5)
+# define BCR_LE				(0x1 << 1)
+# define BCR_WPD			(0x1 << 0)
+# else
 #define BIOS_CNTL		0xdc
 #define  BIOS_CNTL_BIOSWE	(1 << 0)
 #define  BIOS_CNTL_BLE		(1 << 1)
 #define  BIOS_CNTL_SMM_BWP	(1 << 5)
+#endif
 
 static void spi_set_smm_only_flashing(bool enable)
 {
-	if (!(CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)))
-		return;
+	#if CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
+		void *smi_cntl = (void *)(SPI_BASE_ADDRESS + SCS);
+		void *bios_cntl = (void *)(SPI_BASE_ADDRESS + BCR);
+		void *bios_status = (void *)(ILB_BASE_ADDRESS + BCS);
+		uint32_t smi_cntl_reg = read32(smi_cntl);
+		uint32_t bios_cntl_reg = read32(bios_cntl);
+		uint32_t bios_status_reg = read32(bios_status);
+		if(enable){
+			bios_cntl_reg |= EISS;
+			bios_cntl_reg |= BCR_LE;
+			bios_cntl_reg &= ~BCR_WPD;
+
+			smi_cntl_reg |= SMIWPEN;
+			smi_cntl_reg |= SMIWPST;
+
+			bios_status_reg |= BCS_SMIWPEN;
+			bios_status_reg |= BCS_SMIWPST;
+		}
+		else{
+			bios_cntl_reg &= ~EISS;
+			bios_cntl_reg &= ~BCR_LE;
+			bios_cntl_reg |= BCR_WPD;
 
-	const pci_devfn_t dev = PCI_DEV(0, 31, 0);
+			smi_cntl_reg &= ~SMIWPEN;
 
+			bios_status_reg &= ~BCS_SMIWPEN;
+			// bios_status_reg &= ~BCS_SMIWPST;
+		}
+		write32(smi_cntl, smi_cntl_reg);
+		write32(bios_cntl, bios_cntl_reg);
+		write32(bios_status, bios_status_reg);
+	# else
+	const pci_devfn_t dev = PCI_DEV(0, 31, 0);
 	uint8_t bios_cntl = pci_read_config8(dev, BIOS_CNTL);
 
 	if (enable) {
 		bios_cntl &= ~BIOS_CNTL_BIOSWE;
 		bios_cntl |= BIOS_CNTL_BLE | BIOS_CNTL_SMM_BWP;
+
 	} else {
 		bios_cntl &= ~(BIOS_CNTL_BLE | BIOS_CNTL_SMM_BWP);
 		bios_cntl |= BIOS_CNTL_BIOSWE;
 	}
 
 	pci_write_config8(dev, BIOS_CNTL, bios_cntl);
+	#endif
 }
 
 static const struct spi_ctrlr spi_ctrlr = {