Merge branch 'master' into new_algorithm

Chia-Network · Apr 29, 2020 · 8ca85ce · 8ca85ce
2 parents 3349b07 + 83c831d
commit 8ca85ce
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diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
@@ -50,7 +50,7 @@ jobs:
         CIBW_ENVIRONMENT_LINUX: "PATH=/project/cmake-3.17.0-Linux-`uname -m`/bin:$PATH BUILD_VDF_CLIENT=N"
         CIBW_REPAIR_WHEEL_COMMAND_MACOS: "pip uninstall -y delocate && pip install git+https://github.com/Chia-Network/delocate.git && delocate-listdeps {wheel} && delocate-wheel -v {wheel} && cp {wheel} {dest_dir} && ls -l {dest_dir} && pwd && ls -l dist"
         CIBW_BEFORE_BUILD_WINDOWS: python -m pip install --upgrade pip && pwd && git clone https://github.com/Chia-Network/mpir_gc_x64.git && ls -l mpir_gc_x64
-        CIBW_REPAIR_WHEEL_COMMAND_WINDOWS: "ls -l mpir_gc_x64 && pip uninstall -y delocate && pip install git+https://github.com/Chia-Network/delocate.git && delocate-wheel -v -i mpir_gc_x64/mpir.dll {wheel} && cp {wheel} {dest_dir} && ls -l {dest_dir} && pwd && ls -l dist && rm -fr mpir_gc_x64"
+        CIBW_REPAIR_WHEEL_COMMAND_WINDOWS: "ls -l mpir_gc_x64 && pip uninstall -y delocate && pip install git+https://github.com/Chia-Network/delocate.git && delocate-wheel -v -i mpir_gc_x64/mpir.dll {wheel} && delocate-wheel -v -i mpir_gc_x64/mpir_gc.dll {wheel} && delocate-wheel -v -i mpir_gc_x64/mpir_broadwell.dll {wheel} && delocate-wheel -v -i mpir_gc_x64/mpir_broadwell_avx.dll {wheel} && delocate-wheel -v -i mpir_gc_x64/mpir_bulldozer.dll {wheel} && delocate-wheel -v -i mpir_gc_x64/mpir_haswell.dll {wheel} && delocate-wheel -v -i mpir_gc_x64/mpir_piledriver.dll {wheel} && delocate-wheel -v -i mpir_gc_x64/mpir_skylake.dll {wheel} && delocate-wheel -v -i mpir_gc_x64/mpir_skylake_avx.dll {wheel} && cp {wheel} {dest_dir} && ls -l {dest_dir} && pwd && ls -l dist && rm -fr mpir_gc_x64"
 
     - name: Upload artifacts
       uses: actions/upload-artifact@v1

diff --git a/src/parameters.h b/src/parameters.h
@@ -29,15 +29,56 @@ extern bool enable_all_instructions;
 bool bChecked=false;
 bool bAVX2=false;
 
+#if defined(__i386) || defined(_M_IX86)
+    #define ARCH_X86
+#elif defined(__x86_64__) || defined(_M_X64)
+    #define ARCH_X64
+#elif (defined(__arm__) && defined(__ARM_ARCH) && __ARM_ARCH >= 5) || (defined(_M_ARM) && _M_ARM >= 5) || defined(__ARM_FEATURE_CLZ) /* ARM (Architecture Version 5) */
+    #define ARCH_ARM
+#endif
+
+#if defined(_WIN64) || defined(_LP64) || defined(__LP64__)
+    #define ARCH_64BIT
+#else
+    #define ARCH_32BIT
+#endif
+
 inline bool hasAVX2()
 {
   if(!bChecked)
   {
     bChecked=true;
-#if defined(__x86_64__)
-    bAVX2=__builtin_cpu_supports("avx2");
+#if defined(ARCH_X86) || defined(ARCH_X64)
+    int info[4] = {0};
+#if defined(_MSC_VER)
+    __cpuid(info, 0x7);
+#elif defined(__GNUC__) || defined(__clang__)
+#if defined(ARCH_X86) && defined(__PIC__)
+    __asm__ __volatile__ (
+                "xchg{l} {%%}ebx, %k1;"
+                "cpuid;"
+                "xchg{l} {%%}ebx, %k1;"
+                : "=a"(info[0]), "=&r"(info[1]), "=c"(info[2]), "=d"(info[3]) : "a"(0x7), "c"(0)
+    );
+#else
+    __asm__ __volatile__ (
+                "cpuid" : "=a"(info[0]), "=b"(info[1]), "=c"(info[2]), "=d"(info[3]) : "a"(0x7), "c"(0)
+    );
+#endif
+#endif
+    const int AVX2 = 1<<5;
+    const int ADX = 1<<19;
+
+    bool avx2bit = ((info[1] & AVX2) == AVX2);
+    bool adxbit = ((info[1] & ADX) == ADX);
+    bAVX2 = avx2bit && adxbit;
+#elif defined(ARCH_ARM)
+    bAVX2 = false;
+#else
+    bAVX2 = false;
 #endif
   }
+
   return bAVX2;
 }