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Merge branch 'isa_uvm_refactorization' into 'main'
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UVM: [MAITENANCE] Improve UVM verification

See merge request ndk/ofm!395
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@jakubcabal
jakubcabal committed Sep 2, 2024
2 parents 02c9f6b + 5b9bb52 commit d53d045
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Showing 219 changed files with 1,628 additions and 2,074 deletions.
10 changes: 5 additions & 5 deletions comp/base/fifo/asfifox/uvm/tbench/env/scoreboard.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -63,18 +63,18 @@ class scoreboard #(ITEM_WIDTH) extends uvm_scoreboard;
compared++;
if (tr_model.compare(tr_dut) == 0) begin
errors++;
$swrite(msg, "\nTransactions doesnt match\n\tMODEL Transaction\n%s\n\n\tDUT Transaction\n%s", tr_model.convert2string(), tr_dut.convert2string());
msg = $sformatf("\nTransactions doesnt match\n\tMODEL Transaction\n%s\n\n\tDUT Transaction\n%s", tr_model.convert2string(), tr_dut.convert2string());
`uvm_error(this.get_full_name(), msg);
end
end
endtask

virtual function void report_phase(uvm_phase phase);
string msg = "\n";
$swrite(msg, "%sCompared/errors: %0d/%0d \n", msg, compared, errors);
$swrite(msg, "%sCount of items inside RX fifo: %d \n", msg, rx_fifo.used());
$swrite(msg, "%sCount of items inside TX fifo: %d \n", msg, tx_fifo.used());
$swrite(msg, "%sErrors : %d \n", msg, errors);
msg = {msg, $sformatf("Compared/errors: %0d/%0d \n", compared, errors)};
msg = {msg, $sformatf("Count of items inside RX fifo: %d \n", rx_fifo.used())};
msg = {msg, $sformatf("Count of items inside TX fifo: %d \n", tx_fifo.used())};
msg = {msg, $sformatf("Errors : %d \n", errors)};

if (errors == 0 && this.used() == 0) begin
`uvm_info(get_type_name(), $sformatf("%s\n\n\t---------------------------------------\n\t---- VERIFICATION SUCCESS ----\n\t---------------------------------------", msg), UVM_NONE)
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2 changes: 1 addition & 1 deletion comp/base/fifo/fifox/uvm/tbench/env/env.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,7 @@ class env #(DATA_WIDTH, STATUS_WIDTH, ITEMS, ALMOST_FULL_OFFSET, ALMOST_EMPTY_OF
m_reset.sync_connect(m_env_mvb_status.reset_sync);

// RX environments connection
m_env_mvb_rx.analysis_port.connect(sc.analysis_imp_mvb_rx.analysis_export);
m_env_mvb_rx.analysis_port.connect(sc.analysis_imp_mvb_rx);

// TX environments connection
m_env_mvb_tx.analysis_port .connect(sc.analysis_imp_mvb_tx );
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11 changes: 5 additions & 6 deletions comp/base/fifo/fifox/uvm/tbench/env/scoreboard.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -8,14 +8,14 @@ class scoreboard #(DATA_WIDTH, STATUS_WIDTH, ITEMS, ALMOST_FULL_OFFSET, ALMOST_E
`uvm_component_utils(uvm_fifox::scoreboard #(DATA_WIDTH, STATUS_WIDTH, ITEMS, ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSET))

// Analysis components.
uvm_common::subscriber #(uvm_logic_vector::sequence_item #(DATA_WIDTH)) analysis_imp_mvb_rx;
uvm_analysis_export #(uvm_logic_vector::sequence_item #(DATA_WIDTH)) analysis_imp_mvb_rx;

uvm_analysis_export #(uvm_logic_vector::sequence_item #(DATA_WIDTH)) analysis_imp_mvb_tx;
uvm_analysis_export #(uvm_logic_vector::sequence_item #(STATUS_WIDTH+2)) analysis_imp_mvb_status;

// Comparer instance
uvm_common::comparer_ordered #(uvm_logic_vector::sequence_item #(DATA_WIDTH)) cmp;
status_comparer #(uvm_logic_vector::sequence_item #(STATUS_WIDTH+2)) status_cmp;
status_comparer #(STATUS_WIDTH) status_cmp;

// Model instance
uvm_pipe::model #(DATA_WIDTH) m_pipe_model;
Expand All @@ -25,6 +25,7 @@ class scoreboard #(DATA_WIDTH, STATUS_WIDTH, ITEMS, ALMOST_FULL_OFFSET, ALMOST_E
function new(string name, uvm_component parent);
super.new(name, parent);

analysis_imp_mvb_rx = new("analysis_imp_mvb_rx", this);
analysis_imp_mvb_tx = new("analysis_imp_mvb_tx", this);
analysis_imp_mvb_status = new("analysis_imp_mvb_status", this);

Expand All @@ -44,12 +45,10 @@ class scoreboard #(DATA_WIDTH, STATUS_WIDTH, ITEMS, ALMOST_FULL_OFFSET, ALMOST_E

function void build_phase(uvm_phase phase);

analysis_imp_mvb_rx = uvm_common::subscriber #(uvm_logic_vector::sequence_item #(DATA_WIDTH))::type_id::create("analysis_imp_mvb_rx", this);

cmp = uvm_common::comparer_ordered #(uvm_logic_vector::sequence_item #(DATA_WIDTH))::type_id::create("cmp", this);
cmp.model_tr_timeout_set(200us);

status_cmp = status_comparer #(uvm_logic_vector::sequence_item #(STATUS_WIDTH+2))::type_id::create("status_cmp", this);
status_cmp = status_comparer #(STATUS_WIDTH)::type_id::create("status_cmp", this);
status_cmp.model_tr_timeout_set(200us);

m_pipe_model = uvm_pipe::model #(DATA_WIDTH)::type_id::create("m_pipe_model", this);
Expand All @@ -60,7 +59,7 @@ class scoreboard #(DATA_WIDTH, STATUS_WIDTH, ITEMS, ALMOST_FULL_OFFSET, ALMOST_E
function void connect_phase(uvm_phase phase);

// Connects input data to the input of the model
analysis_imp_mvb_rx.port.connect(m_pipe_model.model_mvb_in.analysis_export);
analysis_imp_mvb_rx.connect(m_pipe_model.model_mvb_in.analysis_export);

// Connects output data of the models
m_pipe_model.model_mvb_out.connect(cmp .analysis_imp_model);
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25 changes: 23 additions & 2 deletions comp/base/fifo/fifox/uvm/tbench/env/status_comparer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -4,13 +4,34 @@

// SPDX-License-Identifier: BSD-3-Clause

class status_comparer #(type CLASS_TYPE) extends uvm_common::comparer_ordered #(CLASS_TYPE);
`uvm_component_param_utils(uvm_fifox::status_comparer #(CLASS_TYPE))
class status_comparer #(int unsigned STATUS_WIDTH) extends uvm_common::comparer_ordered #(uvm_logic_vector::sequence_item #(STATUS_WIDTH+2));
`uvm_component_param_utils(uvm_fifox::status_comparer #(STATUS_WIDTH))

function new(string name, uvm_component parent = null);
super.new(name, parent);
endfunction


function string model_item2string(uvm_logic_vector::sequence_item #(STATUS_WIDTH+2) tr);
logic [STATUS_WIDTH-1:0] status;
logic afull;
logic aempty;

{ status, afull, aempty } = tr.data;

return $sformatf("\nStatus\n%s\n\tITEMS %0d\n\tAlmoust full %b\n\tAlmoust full %b", tr.time2string(), status, afull, aempty);
endfunction

function string dut_item2string(uvm_logic_vector::sequence_item #(STATUS_WIDTH+2) tr);
logic [STATUS_WIDTH-1:0] status;
logic afull;
logic aempty;

{ status, afull, aempty } = tr.data;

return $sformatf("\nStatus\n%s\n\tITEMS %0d\n\tAlmoust full %b\n\tAlmoust full %b", tr.time2string(), status, afull, aempty);
endfunction

function void check_phase(uvm_phase phase);
flush();
endfunction
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19 changes: 9 additions & 10 deletions comp/base/fifo/fifox/uvm/tbench/env/status_model.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ class status_model #(STATUS_WIDTH, ITEMS, ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSE
uvm_probe::cbs_simple #(2) wr_and_rd_en_in;

// Model outputs
uvm_analysis_port #(uvm_common::model_item #(uvm_logic_vector::sequence_item #(STATUS_WIDTH+2))) model_out;
uvm_analysis_port #(uvm_logic_vector::sequence_item #(STATUS_WIDTH+2)) model_out;

function new(string name = "status_model", uvm_component parent = null);
super.new(name, parent);
Expand All @@ -30,7 +30,7 @@ class status_model #(STATUS_WIDTH, ITEMS, ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSE

task run_phase(uvm_phase phase);

uvm_common::model_item #(uvm_logic_vector::sequence_item #(STATUS_WIDTH+2)) tr_out;
uvm_logic_vector::sequence_item #(STATUS_WIDTH+2) tr_out;

int unsigned status = 0;

Expand All @@ -43,19 +43,18 @@ class status_model #(STATUS_WIDTH, ITEMS, ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSE

forever begin

wr_and_rd_en_in.get({ wr_en, rd_en });
if (wr_en) status++;
if (rd_en) status--;

logic_status = status;
afull = (status >= ITEMS - ALMOST_FULL_OFFSET) ? 1 : 0;
aempty = (status <= ALMOST_EMPTY_OFFSET) ? 1 : 0;

tr_out = uvm_common::model_item #(uvm_logic_vector::sequence_item #(STATUS_WIDTH+2))::type_id::create("tr_out");
tr_out.item = uvm_logic_vector::sequence_item #(STATUS_WIDTH+2)::type_id::create("tr_out.item");
tr_out.item.data = { logic_status, afull, aempty };
tr_out = uvm_logic_vector::sequence_item #(STATUS_WIDTH+2)::type_id::create("tr_out", this);
tr_out.data = { logic_status, afull, aempty };
tr_out.start[this.get_full_name()] = $time();
model_out.write(tr_out);

wr_and_rd_en_in.get({ wr_en, rd_en });
if (wr_en) status++;
if (rd_en) status--;

end

endtask
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2 changes: 1 addition & 1 deletion comp/base/fifo/fifox_multi/uvm/tbench/env/env.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -107,7 +107,7 @@ class env #(DATA_WIDTH, ITEMS, WRITE_PORTS, READ_PORTS, ALMOST_FULL_OFFSET, ALMO
m_reset.sync_connect(m_env_mvb_status.reset_sync);

// RX environments connection
m_env_mvb_rx.analysis_port.connect(sc.analysis_imp_mvb_rx.analysis_export);
m_env_mvb_rx.analysis_port.connect(sc.analysis_imp_mvb_rx);

// TX environments connection
m_env_mvb_tx.analysis_port.connect(sc.analysis_imp_mvb_tx);
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11 changes: 5 additions & 6 deletions comp/base/fifo/fifox_multi/uvm/tbench/env/scoreboard.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -8,14 +8,14 @@ class scoreboard #(DATA_WIDTH, ITEMS, WRITE_PORTS, READ_PORTS, ALMOST_FULL_OFFSE
`uvm_component_utils(uvm_fifox_multi::scoreboard #(DATA_WIDTH, ITEMS, WRITE_PORTS, READ_PORTS, ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSET, IMPL_SHAKEDOWN))

// Analysis components.
uvm_common::subscriber #(uvm_logic_vector::sequence_item #(DATA_WIDTH)) analysis_imp_mvb_rx;
uvm_analysis_export #(uvm_logic_vector::sequence_item #(DATA_WIDTH)) analysis_imp_mvb_rx;

uvm_analysis_export #(uvm_logic_vector::sequence_item #(DATA_WIDTH)) analysis_imp_mvb_tx;
uvm_analysis_export #(uvm_logic_vector::sequence_item #(2)) analysis_imp_mvb_status;

// Comparer instance
uvm_common::comparer_ordered #(uvm_logic_vector::sequence_item #(DATA_WIDTH)) cmp;
uvm_fifox::status_comparer #(uvm_logic_vector::sequence_item #(2)) status_cmp;
uvm_fifox::status_comparer #(0) status_cmp;

// Model instance
uvm_pipe::model #(DATA_WIDTH) m_pipe_model;
Expand All @@ -25,6 +25,7 @@ class scoreboard #(DATA_WIDTH, ITEMS, WRITE_PORTS, READ_PORTS, ALMOST_FULL_OFFSE
function new(string name, uvm_component parent);
super.new(name, parent);

analysis_imp_mvb_rx = new("analysis_imp_mvb_rx", this);
analysis_imp_mvb_tx = new("analysis_imp_mvb_tx", this);
if (!IMPL_SHAKEDOWN) analysis_imp_mvb_status = new("analysis_imp_mvb_status", this);

Expand All @@ -44,15 +45,13 @@ class scoreboard #(DATA_WIDTH, ITEMS, WRITE_PORTS, READ_PORTS, ALMOST_FULL_OFFSE

function void build_phase(uvm_phase phase);

analysis_imp_mvb_rx = uvm_common::subscriber #(uvm_logic_vector::sequence_item #(DATA_WIDTH))::type_id::create("analysis_imp_mvb_rx", this);

cmp = uvm_common::comparer_ordered #(uvm_logic_vector::sequence_item #(DATA_WIDTH))::type_id::create("cmp", this);
cmp.model_tr_timeout_set(200us);

m_pipe_model = uvm_pipe::model #(DATA_WIDTH)::type_id::create("m_pipe_model", this);

if (!IMPL_SHAKEDOWN) begin
status_cmp = uvm_fifox::status_comparer #(uvm_logic_vector::sequence_item #(2))::type_id::create("status_cmp", this);
status_cmp = uvm_fifox::status_comparer #(0)::type_id::create("status_cmp", this);
status_cmp.model_tr_timeout_set(200us);

m_status_model = status_model #(ITEMS, WRITE_PORTS, READ_PORTS, ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSET)::type_id::create("m_status_model", this);
Expand All @@ -63,7 +62,7 @@ class scoreboard #(DATA_WIDTH, ITEMS, WRITE_PORTS, READ_PORTS, ALMOST_FULL_OFFSE
function void connect_phase(uvm_phase phase);

// Connects input data to the input of the model
analysis_imp_mvb_rx.port.connect(m_pipe_model.model_mvb_in.analysis_export);
analysis_imp_mvb_rx.connect(m_pipe_model.model_mvb_in.analysis_export);

// Connects output data of the models
m_pipe_model.model_mvb_out.connect(cmp.analysis_imp_model);
Expand Down
18 changes: 9 additions & 9 deletions comp/base/fifo/fifox_multi/uvm/tbench/env/status_model.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ class status_model #(ITEMS, WRITE_PORTS, READ_PORTS, ALMOST_FULL_OFFSET, ALMOST_
uvm_probe::cbs_simple #(1+$clog2(WRITE_PORTS+1)+$clog2(READ_PORTS+1)) status_in;

// Model outputs
uvm_analysis_port #(uvm_common::model_item #(uvm_logic_vector::sequence_item #(2))) model_out;
uvm_analysis_port #(uvm_logic_vector::sequence_item #(2)) model_out;

function new(string name = "status_model", uvm_component parent = null);
super.new(name, parent);
Expand All @@ -30,7 +30,7 @@ class status_model #(ITEMS, WRITE_PORTS, READ_PORTS, ALMOST_FULL_OFFSET, ALMOST_

task run_phase(uvm_phase phase);

uvm_common::model_item #(uvm_logic_vector::sequence_item #(2)) tr_out;
uvm_logic_vector::sequence_item #(2) tr_out;

logic afull;
logic aempty;
Expand All @@ -52,9 +52,9 @@ class status_model #(ITEMS, WRITE_PORTS, READ_PORTS, ALMOST_FULL_OFFSET, ALMOST_
afull = (status_wr + wr >= ITEMS - ALMOST_FULL_OFFSET) ? 1 : 0;
aempty = (status_rd[$] - rd <= ALMOST_EMPTY_OFFSET) ? 1 : 0;

tr_out = uvm_common::model_item #(uvm_logic_vector::sequence_item #(2))::type_id::create("tr_out");
tr_out.item = uvm_logic_vector::sequence_item #(2)::type_id::create("tr_out.item");
tr_out.item.data = { afull, aempty };
tr_out = uvm_logic_vector::sequence_item #(2)::type_id::create("tr_out", this);
tr_out.data = { afull, aempty };
tr_out.start[this.get_full_name()] = $time();
model_out.write(tr_out);

// Updates the read status
Expand All @@ -72,10 +72,10 @@ class status_model #(ITEMS, WRITE_PORTS, READ_PORTS, ALMOST_FULL_OFFSET, ALMOST_

task send_initial_transactions();

uvm_common::model_item #(uvm_logic_vector::sequence_item #(2)) tr_out;
tr_out = uvm_common::model_item #(uvm_logic_vector::sequence_item #(2))::type_id::create("tr_out");
tr_out.item = uvm_logic_vector::sequence_item #(2)::type_id::create("tr_out.item");
tr_out.item.data = { 1'b0, 1'b1 };
uvm_logic_vector::sequence_item #(2) tr_out;
tr_out = uvm_logic_vector::sequence_item #(2)::type_id::create("tr_out", this);
tr_out.data = { 1'b0, 1'b1 };
tr_out.start[this.get_full_name()] = $time();
model_out.write(tr_out);

endtask
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2 changes: 1 addition & 1 deletion comp/debug/busreplay/ver_replay/tbench/test.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ program TEST (
task configDesign();
int ret;
string params;
$swrite(params, "-w %s", "dump.txt"); // EDIT THIS: change file path!
params = $sformatf("-w %s", "dump.txt"); // EDIT THIS: change file path!
dpiwait(0, 1); // synchronization
dpicall("busreplay", params, ret);
endtask
Expand Down
4 changes: 2 additions & 2 deletions comp/dma/dma_calypte/comp/rx/uvm/tbench/env/model.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -368,11 +368,11 @@ class model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_component;

// Check whether packet is accepted or not
if (pkt_drop) begin
$swrite(msg, "\n\t\nPacket Dropped:\n RX CHANNEL: %0d\n META: %h\n PACKET SIZE: %0d\n%s", info.channel, info.meta, info.packet_size, tr.convert2string());
msg = $sformatf("\n\t\nPacket Dropped:\n RX CHANNEL: %0d\n META: %h\n PACKET SIZE: %0d\n%s", info.channel, info.meta, info.packet_size, tr.convert2string());
`uvm_info(this.get_full_name(), msg, UVM_MEDIUM);
end else begin
packets_processed++;
$swrite(msg, "\n\t\nPacket Accepted:\n RX CHANNEL: %0d\n META: %h\n PACKET SIZE: %0d\n%s", info.channel, info.meta, info.packet_size, tr.convert2string());
msg = $sformatf("\n\t\nPacket Accepted:\n RX CHANNEL: %0d\n META: %h\n PACKET SIZE: %0d\n%s", info.channel, info.meta, info.packet_size, tr.convert2string());
`uvm_info(this.get_full_name(), msg, UVM_MEDIUM);
packet_send(tr.data, info.input_time, info.channel, info.meta);
end
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14 changes: 7 additions & 7 deletions comp/dma/dma_calypte/comp/rx/uvm/tbench/env/scoreboard.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -247,22 +247,22 @@ class scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_score
$cast(packet_model, tr_model);

compared++;
$swrite(msg, "\nSegments errors/compared : %0d/%0d Packet num %0d", errors, compared, packet_model.packet_num);
msg = $sformatf("\nSegments errors/compared : %0d/%0d Packet num %0d", errors, compared, packet_model.packet_num);

if (!((m_regmodel.channel[packet_model.channel].status.get() & 32'h1 ) | (m_regmodel.channel[packet_model.channel].control.get() & 32'h1))) begin
$swrite(msg, "%s\nReceived packet on stopped channel Packet is:\n\t\tPart is : %s\n\t\tChannel : %0d\n\t\tPart %0d/%0d", msg, packet_model.data_packet == 1 ? "DATA" : "HEADER", packet_model.channel, packet_model.part, packet_model.part_num);
msg = {msg, $sformatf("\nReceived packet on stopped channel Packet is:\n\t\tPart is : %s\n\t\tChannel : %0d\n\t\tPart %0d/%0d", packet_model.data_packet == 1 ? "DATA" : "HEADER", packet_model.channel, packet_model.part, packet_model.part_num)};
`uvm_error(this.get_full_name(), msg);
end

if (pcie_compare(tr_dut.item, tr_dut.meta, packet_model, tr_meta_model) == 0) begin
errors++;

$swrite(msg, "%s\nExpected transaction is:\n\t\tPart is : %s\n\t\tChannel : %0d\n\t\tPart %0d/%0d\n\t\tInput time : %dns", msg, packet_model.data_packet == 1 ? "DATA" : "HEADER", packet_model.channel, packet_model.part, packet_model.part_num, packet_model.start_time/1ns);
msg = {msg, $sformatf("\nExpected transaction is:\n\t\tPart is : %s\n\t\tChannel : %0d\n\t\tPart %0d/%0d\n\t\tInput time : %dns", packet_model.data_packet == 1 ? "DATA" : "HEADER", packet_model.channel, packet_model.part, packet_model.part_num, packet_model.start_time/1ns)};
msg = $sformatf("%s\nMODEL transaction%s\nDUT Transaction%s", msg, tr_model.convert2string(), tr_dut.item.convert2string());
msg = $sformatf("%s\nMODEL META%s\nDUT META%s\n\tDUT doesnt match MODEL transaction", msg, tr_meta_model.convert2string(), tr_dut.meta.convert2string());
`uvm_error(this.get_full_name(), msg);
end else begin
$swrite(msg, "%s\nRecive correct transaction :\n\t\tPart is : %s\n\t\tChannel : %0d\n\t\tPart %0d/%0d\n\t\tPart is delay from SOF on input %0dns", msg, packet_model.data_packet == 1 ? "DATA" : "HEADER", packet_model.channel, packet_model.part, packet_model.part_num, (tr_dut.output_time - packet_model.start_time)/1ns);
msg = {msg, $sformatf("\nRecive correct transaction :\n\t\tPart is : %s\n\t\tChannel : %0d\n\t\tPart %0d/%0d\n\t\tPart is delay from SOF on input %0dns", packet_model.data_packet == 1 ? "DATA" : "HEADER", packet_model.channel, packet_model.part, packet_model.part_num, (tr_dut.output_time - packet_model.start_time)/1ns)};
`uvm_info(this.get_full_name(), $sformatf("%s\nTransaction%s", msg, tr_model.convert2string()), UVM_MEDIUM);
end

Expand All @@ -285,11 +285,11 @@ class scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_score
string str = "";

m_delay.count(min, max, avg, std_dev);
$swrite(str, "%s\n\tDelay statistic (SOF to SOF) => min : %0dns, max : %0dns, avearge : %0dns, standard deviation : %0dns", str, min, max, avg, std_dev);
str = {str, $sformatf("\n\tDelay statistic (SOF to SOF) => min : %0dns, max : %0dns, avearge : %0dns, standard deviation : %0dns", min, max, avg, std_dev)};
m_input_speed.count(min, max, avg, std_dev);
$swrite(str, "%s\n\tSpeed input statistic (MFB RX) => min : %0dGb/s, max : %0dGb/s, avearge : %0dG/s, standard deviation : %0dG/s", str, min*8, max*8, avg*8, std_dev*8);
str = {str, $sformatf("\n\tSpeed input statistic (MFB RX) => min : %0dGb/s, max : %0dGb/s, avearge : %0dG/s, standard deviation : %0dG/s", min*8, max*8, avg*8, std_dev*8)};
m_output_speed.count(min, max, avg, std_dev);
$swrite(str, "%s\n\tSpeed output statistic (PCIE TX) => min : %0dGb/s, max : %0dGb/s, avearge : %0dG/s, standard deviation : %0dG/s", str, min*8, max*8, avg*8, std_dev*8);
str = {str, $sformatf("\n\tSpeed output statistic (PCIE TX) => min : %0dGb/s, max : %0dGb/s, avearge : %0dG/s, standard deviation : %0dG/s", min*8, max*8, avg*8, std_dev*8)};
if (errors == 0) begin
`uvm_info(this.get_full_name(), {str, "\n\n\t---------------------------------------\n\t---- VERIFICATION SUCCESS ----\n\t---------------------------------------"}, UVM_NONE)
end else begin
Expand Down
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