Merge branch 'valek-feat-tx_dma_calypte_two_regions' into 'main'

TX_DMA_CALYPTE [FEATURE]: add support for 2 regions on CQ MFB bus

See merge request ndk/ofm!406

build/Vivado.inc.tcl

@@ -136,6 +136,8 @@ proc SetupDesign {synth_flags} {
     # Manual compile order (automatic is buggy in Vivado)
     set_property source_mgmt_mode DisplayOnly [current_project]
 
+    set_param messaging.defaultLimit 3000
+
     # Apply user settings
     foreach i $SYNTH_FLAGS(SETUP_FLAGS) {
         if { $i == "USE_XPM_LIBRARIES" } {

build/Vivado_non_prj.inc.tcl

@@ -527,6 +527,8 @@ proc SynthesizeProject {synth_flags hierarchy} {
         nb_main
     }
 
+    set_param messaging.defaultLimit 3000
+
     puts "Using FPGA part: $SYNTH_FLAGS(FPGA)"
     set_part $SYNTH_FLAGS(FPGA)
 

build/scripts/multi_synth/synth_parse.py

@@ -148,13 +148,14 @@ def append_proc(proc, text):
 
         # Vivado values parsing
         # synthesis
-        v_syn_llut = grep("LUT as Logic  ", d + vivado_syn_util, 6, 12)
-        v_syn_mlut = grep("LUT as Memory ", d + vivado_syn_util, 6, 12)
-        v_syn_reg = grep("CLB Registers ", d + vivado_syn_util, 5, 11)
-        v_syn_carry = grep("CARRY8        ", d + vivado_syn_util, 4, 10)
-        v_syn_bram = grep("Block RAM Tile", d + vivado_syn_util, 6, 12)
-        v_syn_uram = grep("URAM          ", d + vivado_syn_util, 4, 10)
-        v_syn_dsp = grep("DSPs          ", d + vivado_syn_util, 4, 10)
+        v_syn_llut = grep("LUT as Logic  ", d + vivado_syn_util, 6, 14)
+        v_syn_mlut = grep("LUT as Memory ", d + vivado_syn_util, 6, 14)
+        v_syn_reg = grep("CLB Registers ", d + vivado_syn_util, 5, 13)
+        v_syn_carry = grep("CARRY8        ", d + vivado_syn_util, 4, 12)
+        v_syn_bram = grep("Block RAM Tile", d + vivado_syn_util, 6, 14)
+        v_syn_uram = grep("URAM          ", d + vivado_syn_util, 4, 12)
+        v_syn_dsp = grep("DSPs          ", d + vivado_syn_util, 4, 12)
+
         # implementation
         v_imp_llut = grep("LUT as Logic  ", d + vivado_imp_util, 6)
         v_imp_llut_proc = grep("LUT as Logic  ", d + vivado_imp_util, 10)

comp/base/fifo/reg_fifo/Modules.tcl

@@ -0,0 +1,10 @@
+# Modules.tcl: Components include script
+# Copyright (C) 2024 CESNET
+# Author(s): Vladislav Valek <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+lappend MOD "$ENTITY_BASE/reg_fifo.vhd"
+
+lappend PACKAGES "$OFM_PATH/comp/base/pkg/math_pack.vhd"
+lappend PACKAGES "$OFM_PATH/comp/base/pkg/type_pack.vhd"

comp/base/fifo/reg_fifo/readme.rst

@@ -0,0 +1,6 @@
+.. _reg_fifo:
+
+Register FIFO
+-------------
+
+.. vhdl:autoentity:: REG_FIFO

comp/base/fifo/reg_fifo/reg_fifo.vhd

@@ -0,0 +1,89 @@
+-- reg_fifo.vhd: a primitive FIFO-like buffer from registers
+-- Copyright (C) 2024 CESNET z.s.p.o.
+-- Author(s): Vladislav Valek  <[email protected]>
+--
+-- SPDX-License-Identifier: BSD-3-Clause
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.type_pack.all;
+use work.math_pack.all;
+
+-- This component is the most primitive FIFO here which is made of registers that buffers data also when the
+-- output TX_DST_RDY is deasserted. In that case, the buffer keeps an output RX_DST_RDY asserted
+-- unless the FIFO is full. If the TX_DST_RDY is asserted, the buffer behaves as a set of register
+-- stages of the size ITEMS.
+--
+-- .. WARNING::
+--    It is advised to use this component only on a very limited amounts of DATA_WIDTH*ITEMS.
+--    Otherwise the consumption of the registers can be huge. For more items, refer to other types
+--    of FIFO.
+--
+entity REG_FIFO is
+
+    generic (
+        -- Bit width of data
+        DATA_WIDTH : natural := 256;
+        ITEMS      : natural := 2;
+        -- If this is true, the input data are directly connected to the output as well as the
+        -- handshaking signals.
+        FAKE_FIFO  : boolean := FALSE);
+
+    port (
+        CLK        : in  std_logic;
+        RST        : in  std_logic;
+
+        RX_DATA    : in  std_logic_vector(DATA_WIDTH-1 downto 0);
+        RX_SRC_RDY : in  std_logic;
+        RX_DST_RDY : out std_logic;
+
+        TX_DATA    : out std_logic_vector(DATA_WIDTH -1 downto 0);
+        TX_SRC_RDY : out std_logic;
+        TX_DST_RDY : in  std_logic);
+
+end entity;
+
+architecture FULL of REG_FIFO is
+
+    signal sb_data    : slv_array_t(ITEMS downto 0)(RX_DATA'range);
+    signal sb_src_rdy : std_logic_vector(ITEMS downto 0);
+    signal sb_dst_rdy : std_logic_vector(ITEMS downto 0);
+
+begin
+
+    fake_buff_g : if (FAKE_FIFO) generate
+        TX_DATA    <= RX_DATA;
+        TX_SRC_RDY <= RX_SRC_RDY;
+        RX_DST_RDY <= TX_DST_RDY;
+    end generate;
+
+    not_fake_buff_g : if (not FAKE_FIFO) generate
+
+        sb_data(0)    <= RX_DATA;
+        sb_src_rdy(0) <= RX_SRC_RDY;
+        RX_DST_RDY    <= sb_dst_rdy(0);
+
+        skid_buff_stages_g : for i in 1 to ITEMS generate
+            skid_buffer_p : process (CLK) is
+            begin
+                if (rising_edge(CLK)) then
+                    if (RST = '1') then
+                        sb_src_rdy(i) <= '0';
+                    elsif (sb_dst_rdy(i-1) = '1') then
+                        sb_data(i)    <= sb_data(i-1);
+                        sb_src_rdy(i) <= sb_src_rdy(i-1);
+                    end if;
+                end if;
+            end process;
+
+            sb_dst_rdy(i-1) <= sb_dst_rdy(i) or (not sb_src_rdy(i));
+        end generate;
+
+        TX_DATA            <= sb_data(ITEMS);
+        TX_SRC_RDY         <= sb_src_rdy(ITEMS);
+        sb_dst_rdy(ITEMS) <= TX_DST_RDY;
+
+    end generate;
+end architecture;

comp/base/fifo/reg_fifo/uvm/Modules.tcl

@@ -0,0 +1,21 @@
+# Modules.tcl: Components include script
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Vladislav Valek <[email protected]>
+
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Set paths
+set SV_UVM_BASE             "$OFM_PATH/comp/uvm"
+set SV_MVB_PIPE_UVM_BASE    "$OFM_PATH/comp/mvb_tools/flow/pipe/uvm"
+
+lappend COMPONENTS [ list "SV_RESET"                "$SV_UVM_BASE/reset"            "FULL"]
+lappend COMPONENTS [ list "SV_MVB_UVM"              "$SV_UVM_BASE/mvb"              "FULL"]
+lappend COMPONENTS [ list "SV_LOGIC_VECTOR_MVB_UVM" "$SV_UVM_BASE/logic_vector_mvb" "FULL"]
+lappend COMPONENTS [ list "SV_MVB_PIPE_UVM"         "$SV_MVB_PIPE_UVM_BASE"         "FULL"]
+
+lappend MOD "$ENTITY_BASE/tbench/env/pkg.sv"
+lappend MOD "$ENTITY_BASE/tbench/tests/pkg.sv"
+
+lappend MOD "$ENTITY_BASE/tbench/dut.sv"
+lappend MOD "$ENTITY_BASE/tbench/property.sv"
+lappend MOD "$ENTITY_BASE/tbench/testbench.sv"

comp/base/fifo/reg_fifo/uvm/signals.fdo

@@ -0,0 +1,10 @@
+# signals.fdo : Include file with signals
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Vladislav Valek <[email protected]>
+
+# SPDX-License-Identifier: BSD-3-Clause
+
+proc all {NAME PATH} {
+    add wave -divider "$NAME"
+    add_wave "-noupdate  -hex"       $PATH/*
+}

comp/base/fifo/reg_fifo/uvm/signals_sig.fdo

@@ -0,0 +1,16 @@
+# signal_sig.fdo : Include file with signals
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Vladislav Valek <[email protected]>
+
+# SPDX-License-Identifier: BSD-3-Clause
+
+source "./signals.fdo"
+
+add wave -divider "REG_FIFO"
+
+add_wave "-noupdate -color yellow -label RST"   /testbench/RST
+add_wave "-noupdate -color yellow -label CLK"   /testbench/CLK
+
+all ALL /testbench/DUT_U/VHDL_DUT_U
+
+config wave -signalnamewidth 1

comp/base/fifo/reg_fifo/uvm/tbench/dut.sv

@@ -0,0 +1,37 @@
+// dut.sv: Design under test
+// Copyright (C) 2024 CESNET z. s. p. o.
+// Author(s): Vladislav Valek <[email protected]>
+
+// SPDX-License-Identifier: BSD-3-Clause
+
+import test::*;
+
+module DUT (
+    input logic CLK,
+    input logic RST,
+    mvb_if.dut_rx mvb_rx,
+    mvb_if.dut_tx mvb_tx
+);
+
+    logic mvb_rx_src_rdy;
+
+    REG_FIFO #(
+        .DATA_WIDTH (DATA_WIDTH),
+        .ITEMS      (ITEMS),
+        .FAKE_FIFO  (FAKE_FIFO)
+    ) VHDL_DUT_U (
+        .CLK        (CLK),
+        .RST        (RST),
+
+        .RX_DATA    (mvb_rx.DATA),
+        .RX_SRC_RDY (mvb_rx_src_rdy),
+        .RX_DST_RDY (mvb_rx.DST_RDY),
+
+        .TX_DATA    (mvb_tx.DATA),
+        .TX_SRC_RDY (mvb_tx.SRC_RDY),
+        .TX_DST_RDY (mvb_tx.DST_RDY)
+    );
+
+    assign mvb_rx_src_rdy = mvb_rx.VLD & mvb_rx.SRC_RDY;
+    assign mvb_tx.VLD = 1;
+endmodule

comp/base/fifo/reg_fifo/uvm/tbench/env/env.sv

@@ -0,0 +1,89 @@
+// env.sv: Verification environment
+// Copyright (C) 2024 CESNET z. s. p. o.
+// Author(s): Vladislav Valek <[email protected]>
+
+// SPDX-License-Identifier: BSD-3-Clause
+
+class env #(DATA_WIDTH, ITEMS) extends uvm_env;
+    `uvm_component_param_utils(uvm_fifo_registered::env #(DATA_WIDTH, ITEMS));
+
+    uvm_reset::agent m_reset;
+
+    uvm_logic_vector_mvb::env_rx #(1, DATA_WIDTH) m_env_mvb_rx;
+    uvm_logic_vector_mvb::env_tx #(1, DATA_WIDTH) m_env_mvb_tx;
+
+    // Coverages
+    uvm_mvb::coverage #(1, DATA_WIDTH) m_cover_mvb_rx;
+    uvm_mvb::coverage #(1, DATA_WIDTH) m_cover_mvb_tx;
+
+    // Scoreboard
+    scoreboard #(DATA_WIDTH, ITEMS) sc;
+    // Virtual sequencer
+    virt_sequencer #(DATA_WIDTH) vscr;
+
+    function new(string name, uvm_component parent);
+        super.new(name, parent);
+        // Creation of the coverages
+        m_cover_mvb_rx     = new("m_cover_mvb_rx");
+        m_cover_mvb_tx     = new("m_cover_mvb_tx");
+    endfunction
+
+    function void build_phase(uvm_phase phase);
+        // Creation of the configuration items
+        uvm_reset::config_item m_config_reset;
+        uvm_logic_vector_mvb::config_item m_config_mvb_rx;
+        uvm_logic_vector_mvb::config_item m_config_mvb_tx;
+
+        // Configuration of the reset
+        m_config_reset                = new;
+        m_config_reset.active         = UVM_ACTIVE;
+        m_config_reset.interface_name = "vif_reset";
+        uvm_config_db #(uvm_reset::config_item)::set(this, "m_reset", "m_config", m_config_reset);
+        // Creation of the reset
+        m_reset = uvm_reset::agent::type_id::create("m_reset", this);
+
+        // Configuration of the m_env_mvb_rx
+        m_config_mvb_rx                = new;
+        m_config_mvb_rx.active         = UVM_ACTIVE;
+        m_config_mvb_rx.interface_name = "vif_mvb_rx";
+        uvm_config_db #(uvm_logic_vector_mvb::config_item)::set(this, "m_env_mvb_rx", "m_config", m_config_mvb_rx);
+        // Creation of the m_env_mvb_rx
+        m_env_mvb_rx = uvm_logic_vector_mvb::env_rx #(1, DATA_WIDTH)::type_id::create("m_env_mvb_rx", this);
+
+        // Configuration of the m_env_mvb_tx
+        m_config_mvb_tx                = new;
+        m_config_mvb_tx.active         = UVM_ACTIVE;
+        m_config_mvb_tx.interface_name = "vif_mvb_tx";
+        uvm_config_db #(uvm_logic_vector_mvb::config_item)::set(this, "m_env_mvb_tx", "m_config", m_config_mvb_tx);
+        // Creation of the m_env_mvb_tx
+        m_env_mvb_tx = uvm_logic_vector_mvb::env_tx #(1, DATA_WIDTH)::type_id::create("m_env_mvb_tx", this);
+
+        // Creation of the scoreboard
+        sc = scoreboard #(DATA_WIDTH, ITEMS)::type_id::create("sc", this);
+        // Creation of the virtual sequencer
+        vscr = virt_sequencer #(DATA_WIDTH)::type_id::create("vscr", this);
+    endfunction
+
+    // Connect agent's ports with ports from scoreboard.
+    function void connect_phase(uvm_phase phase);
+
+        // Connection of the reset
+        m_reset.sync_connect(m_env_mvb_rx    .reset_sync);
+        m_reset.sync_connect(m_env_mvb_tx    .reset_sync);
+
+        // RX environments connection
+        m_env_mvb_rx.analysis_port.connect(sc.analysis_imp_mvb_rx);
+
+        // TX environments connection
+        m_env_mvb_tx.analysis_port.connect(sc.analysis_imp_mvb_tx);
+
+        // Connections of the coverages
+        m_env_mvb_rx    .m_mvb_agent.analysis_port.connect(m_cover_mvb_rx    .analysis_export);
+        m_env_mvb_tx    .m_mvb_agent.analysis_port.connect(m_cover_mvb_tx    .analysis_export);
+
+        // Passing the sequencers to the virtual sequencer
+        vscr.m_reset = m_reset.m_sequencer;
+        vscr.m_mvb_rx_sqr = m_env_mvb_rx.m_sequencer;
+        vscr.m_mvb_tx_sqr = m_env_mvb_tx.m_sequencer;
+    endfunction
+endclass

comp/base/fifo/reg_fifo/uvm/tbench/env/pkg.sv

@@ -0,0 +1,21 @@
+// pkg.sv: Package for environment
+// Copyright (C) 2024 CESNET z. s. p. o.
+// Author(s): Vladislav Valek <[email protected]>
+
+// SPDX-License-Identifier: BSD-3-Clause
+
+`ifndef FIFO_REGISTERED_ENV_SV
+`define FIFO_REGISTERED_ENV_SV
+
+package uvm_fifo_registered;
+
+    `include "uvm_macros.svh"
+    import uvm_pkg::*;
+
+    `include "sequencer.sv"
+    `include "scoreboard.sv"
+    `include "env.sv"
+
+endpackage
+
+`endif