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Early data #1

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merged 3 commits into from
Nov 13, 2023
Merged

Early data #1

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26c1795
combined early resp for RdBlk/M/S
mysoreanoop Nov 11, 2023
c54cf39
missing early path response
mysoreanoop Nov 11, 2023
228fd3e
missing transitions
mysoreanoop Nov 11, 2023
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154 changes: 94 additions & 60 deletions src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
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Original file line number Diff line number Diff line change
Expand Up @@ -450,52 +450,57 @@ machine(MachineType:Directory, "AMD Baseline protocol")
}

action(s_sendResponseS, "s", desc="send Shared response") {
enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:NBSysResp;
if (tbe.L3Hit) {
out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0));
} else {
out_msg.Sender := machineID;
if(!tbe.responded) {
enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:NBSysResp;
if (tbe.L3Hit) {
out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0));
} else {
out_msg.Sender := machineID;
}
out_msg.Destination.add(tbe.OriginalRequestor);
out_msg.DataBlk := tbe.DataBlk;
out_msg.MessageSize := MessageSizeType:Response_Data;
out_msg.Dirty := false;
out_msg.State := CoherenceState:Shared;
out_msg.InitialRequestTime := tbe.InitialRequestTime;
out_msg.ForwardRequestTime := tbe.ForwardRequestTime;
out_msg.ProbeRequestStartTime := tbe.ProbeRequestStartTime;
out_msg.OriginalResponder := tbe.LastSender;
out_msg.L3Hit := tbe.L3Hit;
DPRINTF(RubySlicc, "%s\n", out_msg);
}
out_msg.Destination.add(tbe.OriginalRequestor);
out_msg.DataBlk := tbe.DataBlk;
out_msg.MessageSize := MessageSizeType:Response_Data;
out_msg.Dirty := false;
out_msg.State := CoherenceState:Shared;
out_msg.InitialRequestTime := tbe.InitialRequestTime;
out_msg.ForwardRequestTime := tbe.ForwardRequestTime;
out_msg.ProbeRequestStartTime := tbe.ProbeRequestStartTime;
out_msg.OriginalResponder := tbe.LastSender;
out_msg.L3Hit := tbe.L3Hit;
DPRINTF(RubySlicc, "%s\n", out_msg);
}
}

action(es_sendResponseES, "es", desc="send Exclusive or Shared response") {
enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:NBSysResp;
if (tbe.L3Hit) {
out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0));
} else {
out_msg.Sender := machineID;
}
out_msg.Destination.add(tbe.OriginalRequestor);
out_msg.DataBlk := tbe.DataBlk;
out_msg.MessageSize := MessageSizeType:Response_Data;
out_msg.Dirty := tbe.Dirty;
if (tbe.Cached) {
out_msg.State := CoherenceState:Shared;
} else {
out_msg.State := CoherenceState:Exclusive;
if(!tbe.responded) {
enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:NBSysResp;
if (tbe.L3Hit) {
out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0));
} else {
out_msg.Sender := machineID;
}
out_msg.Destination.add(tbe.OriginalRequestor);
out_msg.DataBlk := tbe.DataBlk;
out_msg.MessageSize := MessageSizeType:Response_Data;
out_msg.Dirty := tbe.Dirty;
// this is ignored by GPU
if (tbe.Cached) {
out_msg.State := CoherenceState:Shared;
} else {
out_msg.State := CoherenceState:Exclusive;
}
out_msg.InitialRequestTime := tbe.InitialRequestTime;
out_msg.ForwardRequestTime := tbe.ForwardRequestTime;
out_msg.ProbeRequestStartTime := tbe.ProbeRequestStartTime;
out_msg.OriginalResponder := tbe.LastSender;
out_msg.L3Hit := tbe.L3Hit;
DPRINTF(RubySlicc, "%s\n", out_msg);
}
out_msg.InitialRequestTime := tbe.InitialRequestTime;
out_msg.ForwardRequestTime := tbe.ForwardRequestTime;
out_msg.ProbeRequestStartTime := tbe.ProbeRequestStartTime;
out_msg.OriginalResponder := tbe.LastSender;
out_msg.L3Hit := tbe.L3Hit;
DPRINTF(RubySlicc, "%s\n", out_msg);
}
}

Expand Down Expand Up @@ -1057,7 +1062,7 @@ machine(MachineType:Directory, "AMD Baseline protocol")
unset_tbe();
}

action(wdm_writeBackDataM, "wdm", desc="Write back data if needed") {
action(wd_writeBackData, "wd", desc="Write back data if needed") {
if (tbe.wtData || tbe.atomicData || tbe.Dirty == false) {
// Only perform atomics in the directory if the SLC bit is set, or
// if the L2 is WT
Expand All @@ -1082,24 +1087,6 @@ machine(MachineType:Directory, "AMD Baseline protocol")
}
}

action(wd_writeBackData, "wd", desc="Write back data if needed") {
if (tbe.wtData || tbe.atomicData || tbe.Dirty == false) {
// Only perform atomics in the directory if the SLC bit is set, or
// if the L2 is WT
if (tbe.atomicData && (tbe.isSLCSet || !L2isWB)) {
tbe.DataBlk.atomicPartial(tbe.DataBlk, tbe.writeMask);
}
enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) {
out_msg.addr := address;
out_msg.Type := MemoryRequestType:MEMORY_WB;
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Data;
out_msg.DataBlk := tbe.DataBlk;
DPRINTF(ProtocolTrace, "%s\n", out_msg);
}
}
}

action(mt_writeMemDataToTBE, "mt", desc="write Mem data to TBE") {
peek(memQueue_in, MemoryMsg) {
if (tbe.wtData == true) {
Expand Down Expand Up @@ -1192,6 +1179,53 @@ machine(MachineType:Directory, "AMD Baseline protocol")
}
}
}
} else if (tbe.TBEState == State:BS_PM || tbe.TBEState == State:BS_Pm) {
enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:NBSysResp;
if (tbe.L3Hit) {
out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0));
} else {
out_msg.Sender := machineID;
}
out_msg.Destination.add(tbe.OriginalRequestor);
out_msg.DataBlk := tbe.DataBlk;
out_msg.MessageSize := MessageSizeType:Response_Data;
out_msg.Dirty := false;
out_msg.State := CoherenceState:Shared;
out_msg.InitialRequestTime := tbe.InitialRequestTime;
out_msg.ForwardRequestTime := tbe.ForwardRequestTime;
out_msg.ProbeRequestStartTime := tbe.ProbeRequestStartTime;
out_msg.OriginalResponder := tbe.LastSender;
out_msg.L3Hit := tbe.L3Hit;
DPRINTF(RubySlicc, "%s\n", out_msg);
}
} else if (tbe.TBEState == State:B_PM || tbe.TBEState == State:B_Pm) {
enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:NBSysResp;
if (tbe.L3Hit) {
out_msg.Sender := createMachineID(MachineType:L3Cache, intToID(0));
} else {
out_msg.Sender := machineID;
}
out_msg.Destination.add(tbe.OriginalRequestor);
out_msg.DataBlk := tbe.DataBlk;
out_msg.MessageSize := MessageSizeType:Response_Data;
out_msg.Dirty := tbe.Dirty;
// this is ignored by GPU
if (tbe.Cached) {
out_msg.State := CoherenceState:Shared;
} else {
out_msg.State := CoherenceState:Exclusive;
}
out_msg.InitialRequestTime := tbe.InitialRequestTime;
out_msg.ForwardRequestTime := tbe.ForwardRequestTime;
out_msg.ProbeRequestStartTime := tbe.ProbeRequestStartTime;
out_msg.OriginalResponder := tbe.LastSender;
out_msg.L3Hit := tbe.L3Hit;
DPRINTF(RubySlicc, "%s\n", out_msg);
}
}
tbe.responded := true;
}
Expand Down Expand Up @@ -1490,7 +1524,7 @@ machine(MachineType:Directory, "AMD Baseline protocol")
}

// there is now a new possibility of core unblocking before all probes/memory is read
transition({BM_M, BM_PM, BM_Pm}, CoreUnblock) {
transition({BM_M, BM_PM, BM_Pm, BS_M, BS_PM, BS_Pm, B_M, B_PM, B_Pm}, CoreUnblock) {
z_stall;
}

Expand Down
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