Revert "Cythonize use of time in RTC"

This reverts commit fab8a2f.
Baekalfen · Nov 30, 2023 · 4bc5bd0 · 4bc5bd0
1 parent 248abde
commit 4bc5bd0
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Showing 2 changed files with 13 additions and 15 deletions.
diff --git a/pyboy/core/cartridge/rtc.pxd b/pyboy/core/cartridge/rtc.pxd
@@ -3,9 +3,6 @@
 # GitHub: https://github.com/Baekalfen/PyBoy
 #
 
-import cython
-
-from cpython cimport time
 from libc.stdint cimport uint8_t, uint16_t, uint64_t
 
 from pyboy cimport utils
@@ -18,7 +15,7 @@ cdef Logger logger
 cdef class RTC:
     cdef str filename
     cdef bint latch_enabled
-    cdef cython.double timezero
+    cdef double timezero
     cdef uint64_t sec_latch
     cdef uint64_t min_latch
     cdef uint64_t hour_latch
@@ -30,9 +27,10 @@ cdef class RTC:
     cdef void stop(self) noexcept
     cdef void save_state(self, IntIOInterface) noexcept
     cdef void load_state(self, IntIOInterface, int) noexcept
+
     @cython.locals(days=uint64_t)
-    cdef void latch_rtc(self) noexcept nogil
+    cdef void latch_rtc(self) noexcept with gil
     cdef void writecommand(self, uint8_t) noexcept nogil
     cdef uint8_t getregister(self, uint8_t) noexcept nogil
     @cython.locals(t=cython.double, days=uint64_t)
-    cdef void setregister(self, uint8_t, uint8_t) noexcept nogil
+    cdef void setregister(self, uint8_t, uint8_t) noexcept with gil
diff --git a/pyboy/core/cartridge/rtc.py b/pyboy/core/cartridge/rtc.py
@@ -46,16 +46,16 @@ def save_state(self, f):
         f.write(self.day_carry)
 
     def load_state(self, f, state_version):
-        self.timezero = int(struct.unpack("f", bytes([f.read() for _ in range(4)]))[0])
+        self.timezero = struct.unpack("f", bytes([f.read() for _ in range(4)]))[0]
         self.halt = f.read()
         self.day_carry = f.read()
 
     def latch_rtc(self):
         t = time.time() - self.timezero
         self.sec_latch = int(t % 60)
-        self.min_latch = int((t//60) % 60)
-        self.hour_latch = int((t//3600) % 24)
-        days = int(t // 3600 // 24)
+        self.min_latch = int(t / 60 % 60)
+        self.hour_latch = int(t / 3600 % 24)
+        days = int(t / 3600 / 24)
         self.day_latch_low = days & 0xFF
         self.day_latch_high = days >> 8
 
@@ -102,13 +102,13 @@ def setregister(self, register, value):
         t = time.time() - self.timezero
         if register == 0x08:
             # TODO: What happens, when these value are larger than allowed?
-            self.timezero = self.timezero - (t%60) - value
+            self.timezero -= int(t % 60) - value
         elif register == 0x09:
-            self.timezero = self.timezero - (t//60%60) - value
+            self.timezero -= int(t / 60 % 60) - value
         elif register == 0x0A:
-            self.timezero = self.timezero - (t//3600%24) - value
+            self.timezero -= int(t / 3600 % 24) - value
         elif register == 0x0B:
-            self.timezero = self.timezero - (t//3600//24) - value
+            self.timezero -= int(t / 3600 / 24) - value
         elif register == 0x0C:
             day_high = value & 0b1
             halt = (value & 0b1000000) >> 6
@@ -120,7 +120,7 @@ def setregister(self, register, value):
             else:
                 logger.warning("Stopping RTC is not implemented!")
 
-            self.timezero = self.timezero - (t//3600//24) - (day_high << 8)
+            self.timezero -= int(t / 3600 / 24) - (day_high << 8)
             self.day_carry = day_carry
         else:
             logger.warning("Invalid RTC register: %0.4x %0.2x", register, value)