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[Fix] Revert L1 cache to CP2- compatible params (256 wordsize, 16 set…
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…s, 4 ways)
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@AllenHeartcore
AllenHeartcore committed Dec 3, 2023
1 parent 1a8ea88 commit f9cb6c0
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Showing 22 changed files with 102 additions and 38 deletions.
12 changes: 6 additions & 6 deletions mp4/apply_cache_params.sh
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@@ -1,10 +1,10 @@
#!/bin/bash

NSET1=4
NWAY1=1
NWAY1=2
NSET2=5
NWAY2=1
WORDSIZE=7
WORDSIZE=8
MULTILV_I_CACHE=0
MULTILV_D_CACHE=0

Expand Down Expand Up @@ -45,10 +45,10 @@ then
word_size = $((2**$WORDSIZE))
write_size = 8
num_words = $((2**$NSET1))
output_name = \"mp3_data_array_1\"
output_name = \"mp3_data_array\"
output_path = \"output/{}\".format(output_name)
" > sram/config/_mp3_array_pt2
cat sram/config/_mp3_array_pt* > sram/config/mp3_data_array_1.py
cat sram/config/_mp3_array_pt* > sram/config/mp3_data_array.py

echo "
word_size = $((2**$WORDSIZE))
Expand All @@ -62,10 +62,10 @@ output_path = \"output/{}\".format(output_name)
echo "
word_size = $((35-$WORDSIZE-$NSET1))
num_words = $((2**$NSET1))
output_name = \"mp3_tag_array_1\"
output_name = \"mp3_tag_array\"
output_path = \"output/{}\".format(output_name)
" > sram/config/_mp3_array_pt2
cat sram/config/_mp3_array_pt* > sram/config/mp3_tag_array_1.py
cat sram/config/_mp3_array_pt* > sram/config/mp3_tag_array.py

echo "
word_size = $((35-$WORDSIZE-$NSET2))
Expand Down
4 changes: 2 additions & 2 deletions mp4/hdl/cache/cache_datapath.sv
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Expand Up @@ -73,7 +73,7 @@ import cache_types::*;
generate for (i = 0; i < num_ways; i++) begin : arrays

if (level == 1) begin
mp3_data_array_1 #(
mp3_data_array #(
.ADDR_WIDTH (s_index),
.DATA_WIDTH (s_word),
.NUM_WMASKS (s_mask)
Expand All @@ -86,7 +86,7 @@ import cache_types::*;
.din0 (DATAMUX ? pmem_rdata : mem_wdata),
.dout0 (data_q[i])
);
mp3_tag_array_1 #(
mp3_tag_array #(
.ADDR_WIDTH (s_index),
.DATA_WIDTH (s_tag)
) tag_array (
Expand Down
4 changes: 2 additions & 2 deletions mp4/pkg/_types_pt2
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@@ -1,8 +1,8 @@

package cache_params_pkg;
parameter CACHE_LOG2_NUMSETS_L1 = 4;
parameter CACHE_LOG2_NUMWAYS_L1 = 1;
parameter CACHE_LOG2_NUMWAYS_L1 = 2;
parameter CACHE_LOG2_NUMSETS_L2 = 5;
parameter CACHE_LOG2_NUMWAYS_L2 = 1;
parameter CACHE_LOG2_WORDSIZE = 7;
parameter CACHE_LOG2_WORDSIZE = 8;

4 changes: 2 additions & 2 deletions mp4/pkg/types.sv
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Expand Up @@ -233,9 +233,9 @@ endpackage : hazard_ctrl_pkg

package cache_params_pkg;
parameter CACHE_LOG2_NUMSETS_L1 = 4;
parameter CACHE_LOG2_NUMWAYS_L1 = 1;
parameter CACHE_LOG2_NUMWAYS_L1 = 2;
parameter CACHE_LOG2_NUMSETS_L2 = 5;
parameter CACHE_LOG2_NUMWAYS_L2 = 1;
parameter CACHE_LOG2_WORDSIZE = 7;
parameter CACHE_LOG2_WORDSIZE = 8;

endpackage : cache_params_pkg
4 changes: 2 additions & 2 deletions mp4/sram/config/mp3_data_array_1.py → mp4/sram/config/mp3_data_array.py
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Original file line number Diff line number Diff line change
Expand Up @@ -24,9 +24,9 @@
num_threads = 4
output_extended_config = True

word_size = 128
word_size = 256
write_size = 8
num_words = 16
output_name = "mp3_data_array_1"
output_name = "mp3_data_array"
output_path = "output/{}".format(output_name)

2 changes: 1 addition & 1 deletion mp4/sram/config/mp3_data_array_2.py
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@
num_threads = 4
output_extended_config = True

word_size = 128
word_size = 256
write_size = 8
num_words = 32
output_name = "mp3_data_array_2"
Expand Down
4 changes: 2 additions & 2 deletions mp4/sram/config/mp3_tag_array_1.py → mp4/sram/config/mp3_tag_array.py
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Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,8 @@
num_threads = 4
output_extended_config = True

word_size = 24
word_size = 23
num_words = 16
output_name = "mp3_tag_array_1"
output_name = "mp3_tag_array"
output_path = "output/{}".format(output_name)

2 changes: 1 addition & 1 deletion mp4/sram/config/mp3_tag_array_2.py
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Expand Up @@ -24,7 +24,7 @@
num_threads = 4
output_extended_config = True

word_size = 23
word_size = 22
num_words = 32
output_name = "mp3_tag_array_2"
output_path = "output/{}".format(output_name)
Expand Down
4 changes: 2 additions & 2 deletions mp4/sram/output/mp3_data_array_1.py → mp4/sram/output/mp3_data_array.py
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Original file line number Diff line number Diff line change
Expand Up @@ -24,9 +24,9 @@
num_threads = 4
output_extended_config = True

word_size = 128
word_size = 256
write_size = 8
num_words = 16
output_name = "mp3_data_array_1"
output_name = "mp3_data_array"
output_path = "output/{}".format(output_name)

40 changes: 36 additions & 4 deletions ...utput/mp3_data_array_1/mp3_data_array_1.v → ...am/output/mp3_data_array/mp3_data_array.v
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
// OpenRAM SRAM model
// Words: 16
// Word size: 128
// Word size: 256
// Write size: 8

module mp3_data_array_1(
module mp3_data_array(
`ifdef USE_POWER_PINS
vdd,
gnd,
Expand All @@ -12,8 +12,8 @@ module mp3_data_array_1(
clk0,csb0,web0,wmask0,addr0,din0,dout0
);

parameter NUM_WMASKS = 16 ;
parameter DATA_WIDTH = 128 ;
parameter NUM_WMASKS = 32 ;
parameter DATA_WIDTH = 256 ;
parameter ADDR_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
Expand Down Expand Up @@ -95,6 +95,38 @@ module mp3_data_array_1(
mem[addr0_reg][119:112] = din0_reg[119:112];
if (wmask0_reg[15])
mem[addr0_reg][127:120] = din0_reg[127:120];
if (wmask0_reg[16])
mem[addr0_reg][135:128] = din0_reg[135:128];
if (wmask0_reg[17])
mem[addr0_reg][143:136] = din0_reg[143:136];
if (wmask0_reg[18])
mem[addr0_reg][151:144] = din0_reg[151:144];
if (wmask0_reg[19])
mem[addr0_reg][159:152] = din0_reg[159:152];
if (wmask0_reg[20])
mem[addr0_reg][167:160] = din0_reg[167:160];
if (wmask0_reg[21])
mem[addr0_reg][175:168] = din0_reg[175:168];
if (wmask0_reg[22])
mem[addr0_reg][183:176] = din0_reg[183:176];
if (wmask0_reg[23])
mem[addr0_reg][191:184] = din0_reg[191:184];
if (wmask0_reg[24])
mem[addr0_reg][199:192] = din0_reg[199:192];
if (wmask0_reg[25])
mem[addr0_reg][207:200] = din0_reg[207:200];
if (wmask0_reg[26])
mem[addr0_reg][215:208] = din0_reg[215:208];
if (wmask0_reg[27])
mem[addr0_reg][223:216] = din0_reg[223:216];
if (wmask0_reg[28])
mem[addr0_reg][231:224] = din0_reg[231:224];
if (wmask0_reg[29])
mem[addr0_reg][239:232] = din0_reg[239:232];
if (wmask0_reg[30])
mem[addr0_reg][247:240] = din0_reg[247:240];
if (wmask0_reg[31])
mem[addr0_reg][255:248] = din0_reg[255:248];
end
end

Expand Down
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Binary file removed mp4/sram/output/mp3_data_array_1/mp3_data_array_1_TT_1p0V_25C_lib.db
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2 changes: 1 addition & 1 deletion mp4/sram/output/mp3_data_array_2.py
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Expand Up @@ -24,7 +24,7 @@
num_threads = 4
output_extended_config = True

word_size = 128
word_size = 256
write_size = 8
num_words = 32
output_name = "mp3_data_array_2"
Expand Down
38 changes: 35 additions & 3 deletions mp4/sram/output/mp3_data_array_2/mp3_data_array_2.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// OpenRAM SRAM model
// Words: 32
// Word size: 128
// Word size: 256
// Write size: 8

module mp3_data_array_2(
Expand All @@ -12,8 +12,8 @@ module mp3_data_array_2(
clk0,csb0,web0,wmask0,addr0,din0,dout0
);

parameter NUM_WMASKS = 16 ;
parameter DATA_WIDTH = 128 ;
parameter NUM_WMASKS = 32 ;
parameter DATA_WIDTH = 256 ;
parameter ADDR_WIDTH = 5 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
Expand Down Expand Up @@ -95,6 +95,38 @@ module mp3_data_array_2(
mem[addr0_reg][119:112] = din0_reg[119:112];
if (wmask0_reg[15])
mem[addr0_reg][127:120] = din0_reg[127:120];
if (wmask0_reg[16])
mem[addr0_reg][135:128] = din0_reg[135:128];
if (wmask0_reg[17])
mem[addr0_reg][143:136] = din0_reg[143:136];
if (wmask0_reg[18])
mem[addr0_reg][151:144] = din0_reg[151:144];
if (wmask0_reg[19])
mem[addr0_reg][159:152] = din0_reg[159:152];
if (wmask0_reg[20])
mem[addr0_reg][167:160] = din0_reg[167:160];
if (wmask0_reg[21])
mem[addr0_reg][175:168] = din0_reg[175:168];
if (wmask0_reg[22])
mem[addr0_reg][183:176] = din0_reg[183:176];
if (wmask0_reg[23])
mem[addr0_reg][191:184] = din0_reg[191:184];
if (wmask0_reg[24])
mem[addr0_reg][199:192] = din0_reg[199:192];
if (wmask0_reg[25])
mem[addr0_reg][207:200] = din0_reg[207:200];
if (wmask0_reg[26])
mem[addr0_reg][215:208] = din0_reg[215:208];
if (wmask0_reg[27])
mem[addr0_reg][223:216] = din0_reg[223:216];
if (wmask0_reg[28])
mem[addr0_reg][231:224] = din0_reg[231:224];
if (wmask0_reg[29])
mem[addr0_reg][239:232] = din0_reg[239:232];
if (wmask0_reg[30])
mem[addr0_reg][247:240] = din0_reg[247:240];
if (wmask0_reg[31])
mem[addr0_reg][255:248] = din0_reg[255:248];
end
end

Expand Down
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4 changes: 2 additions & 2 deletions mp4/sram/output/mp3_tag_array_1.py → mp4/sram/output/mp3_tag_array.py
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Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,8 @@
num_threads = 4
output_extended_config = True

word_size = 24
word_size = 23
num_words = 16
output_name = "mp3_tag_array_1"
output_name = "mp3_tag_array"
output_path = "output/{}".format(output_name)

8 changes: 4 additions & 4 deletions .../output/mp3_tag_array_1/mp3_tag_array_1.v → ...sram/output/mp3_tag_array/mp3_tag_array.v
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
// OpenRAM SRAM model
// Words: 16
// Word size: 24
// Word size: 23

module mp3_tag_array_1(
module mp3_tag_array(
`ifdef USE_POWER_PINS
vdd,
gnd,
Expand All @@ -11,7 +11,7 @@ module mp3_tag_array_1(
clk0,csb0,web0,addr0,din0,dout0
);

parameter DATA_WIDTH = 24 ;
parameter DATA_WIDTH = 23 ;
parameter ADDR_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
Expand Down Expand Up @@ -58,7 +58,7 @@ module mp3_tag_array_1(
always @ (negedge clk0)
begin : MEM_WRITE0
if ( !csb0_reg && !web0_reg ) begin
mem[addr0_reg][23:0] = din0_reg[23:0];
mem[addr0_reg][22:0] = din0_reg[22:0];
end
end

Expand Down
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2 changes: 1 addition & 1 deletion mp4/sram/output/mp3_tag_array_2.py
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Expand Up @@ -24,7 +24,7 @@
num_threads = 4
output_extended_config = True

word_size = 23
word_size = 22
num_words = 32
output_name = "mp3_tag_array_2"
output_path = "output/{}".format(output_name)
Expand Down
6 changes: 3 additions & 3 deletions mp4/sram/output/mp3_tag_array_2/mp3_tag_array_2.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// OpenRAM SRAM model
// Words: 32
// Word size: 23
// Word size: 22

module mp3_tag_array_2(
`ifdef USE_POWER_PINS
Expand All @@ -11,7 +11,7 @@ module mp3_tag_array_2(
clk0,csb0,web0,addr0,din0,dout0
);

parameter DATA_WIDTH = 23 ;
parameter DATA_WIDTH = 22 ;
parameter ADDR_WIDTH = 5 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
Expand Down Expand Up @@ -58,7 +58,7 @@ module mp3_tag_array_2(
always @ (negedge clk0)
begin : MEM_WRITE0
if ( !csb0_reg && !web0_reg ) begin
mem[addr0_reg][22:0] = din0_reg[22:0];
mem[addr0_reg][21:0] = din0_reg[21:0];
end
end

Expand Down
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