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Aatib-cpu/README.md
  • 👋 Hi, I’m Aatib
  • 👀 I’m interested in RTL Design Engineer
  • 🌱 I’m currently learning Verilog
  • 💞️ I’m looking to collaborate VLSI architecture
  • 📫 My Email Id: [email protected]
  • 😄 Pronouns: ...
  • ⚡ Fun fact: ...

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    Config files for my GitHub profile.