Serialized, multifunction headstage for small rodents. Designed to function with eib-64.
{% include gerber_layers.md %}
The BOM is located on this google sheet.
The FPGA pinout is located on this google sheet.
The headstage connector pinout (ADC input mapping, stimulation connections, etc) is located on this google sheet
Copyright Jonathan P. Newman, Jakob Voigts 2017.
This documentation describes Open Hardware and is licensed under the CERN OHL v.1.2.
You may redistribute and modify this documentation under the terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.2 for applicable conditions