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PCIeScreamer blog post #465

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IgorBagnucki
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Signed-off-by: Igor Bagnucki [email protected]

@IgorBagnucki IgorBagnucki changed the title WIP: 2022-01-03-pcie_screamer.md: Add intro to blog-post PCIeScreamer blog pos Jan 4, 2022
@IgorBagnucki IgorBagnucki changed the title PCIeScreamer blog pos PCIeScreamer blog post Jan 4, 2022
@macpijan macpijan self-requested a review January 27, 2022 12:00

Because PCIeScreamer uses Xilinx FPGA, it needs the later one.

## Vavado installation problem
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Suggested change
## Vavado installation problem
## Vivado installation problem

be tested, or in other words, it should be tried to make such an attack on a
system.

## What is PCIeScreamer
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@mgabryelski1 mgabryelski1 Apr 28, 2022

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In my opinion there is lack of information what version of "PCIScreamer" had been used in experiment. There are two majot versions of this device: version2 and version 4. On photos posted on project WWW page one can see that JTAG headers a not soldered.

./pcie_screamer.py --build
```

4. However, the loading fails

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There is lack of information what type of hardware programer had been used. Was it JTAG programmer : "Xilinx Cable" of one of it's clones, or maybe one of serial programmers (USB2serial).

OSError: Error occured during OpenOCD's call, please check:
- OpenOCD installation.
- access permissions.
- hardware and cable.

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Having JTAG header soldered on PCIScreamer board one can use JTAG programmer for Xilinx FPGAs (best Xilinx Cable) for uploading binary configuration file into board. For this purpose "Vivado Hardware Manager" can be used. As far as I understand configuration file for FPGA was created in earlier step.

- OpenOCD installation.
- access permissions.
- hardware and cable.
```

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I found on this github page project containing HDL language(System Verilog) sources for PCIScreamer. Her is link to his repository:
PCIScreamer

In this repository are included all source file (with all needed IPCores) and TCL scripts for building project in "Xilinx Vivad". Having project sources in HDL language also let to synthesize configuration file for FPGA chip.

![](/img/PCIeScreamer_LED.jpg)

The incorrect power delivered to the FPGA could be the result of the faulty PCIe
low-profile riser card used to connect the PCIeScreamer to the motherboard.

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Yes powering problem is quite likely, especially that these PCIScreamers boards are known of their stability issues. Here is citation from project page:

The PCIeScreamer R01 is known to have stability issues. The PCILeech/LeechCore have some mitigations built into the v3.2 version of the bitstream to mitigate as much as possible. If using the R01 version of the PCIeScreamer use the v3.2 version of the bitstream. The PCIe link to the target system may experience instability, degradation or total loss of connectivity in some cases. In some cases the link intermittently becomes unavailable resulting in lost DMA/TLP packets.

FPGA didn't work, and if it is correctly connected.
This work should include checking the FPGA with a different motherboard,
preferably without a low-profile riser card. If that doesn't help, another JTAG
programmer may solve the problem.
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@mgabryelski1 mgabryelski1 Apr 28, 2022

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In my opinion we should try again to upload configuration file into PCIScreamer using tested JTAG programmer and Viavado tools for programming FPGA. There is also alternative to synthesize project from sources in "System Verilog" and using Vivado as major toll for this purpose. From attached to blog photo I guess taht it was version 4 of PCIScreamer and JTAG header has been soldered.

@@ -0,0 +1,218 @@
---
title: PCIe Screamer first look
abstract: 'Abstract first sentence.
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missing abstract

Abstract second sentence.
Abstract third sentence.'
cover: /covers/PCIExpress.jpg
author: igor.bagnucki
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@mgabryelski1 if you will update/add new sections to blog post, please add yourself like in this example: https://github.com/3mdeb/news-and-ideas#single-or-multiple-authors

- sniffing
- pci
- fpga
categories:
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max 2-3 categories should be left

mgabryelski1 and others added 14 commits August 30, 2022 12:35
@artur-rs artur-rs changed the base branch from master to develop September 26, 2022 14:33
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@macpijan @mgabryelski1 images added in this PR that are not used in the blog post:

  • blog/static/img/PCIeScreamer_LED.jpg
  • blog/static/img/PCIeScreamer_Adapter.jpg

If it's inteded, then please remove the files from this PR, otherwise add in the correct section.

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5 participants