[on hold] WIP: Istep 6 11

src/include/cpu/power/istep_6.h

@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <commonlib/region.h>
+#include <cpu/power/scom.h>
+#include <types.h>
+
+void istep_6_11(void);
+
+#define FREQ_PB_MHZ (1866)
+
+#define MASTER_PROC (1)
+
+#define OCC_FW0                     (0)
+#define OCC_FW1                     (1)
+#define CME_ERR_NOTIFY              (2)
+#define STOP_RCV_NOTIFY_PRD         (3)
+#define OCC_HB_NOTIFY               (4)
+#define GPE0_WD_TIMEOUT             (5)
+#define GPE1_WD_TIMEOUT             (6)
+#define GPE2_WD_TIMEOUT             (7)
+#define GPE3_WD_TIMEOUT             (8)
+#define GPE0_ERR                    (9)
+#define GPE1_ERR                    (10)
+#define GPE2_ERR                    (11)
+#define GPE3_ERR                    (12)
+#define OCB_ERR                     (13)
+#define SRAM_UE                     (14)
+#define SRAM_CE                     (15)
+#define SRAM_READ_ERR               (16)
+#define SRAM_WRITE_ERR              (17)
+#define SRAM_DATAOUT_PERR           (18)
+#define SRAM_OCI_WDATA_PARITY       (19)
+#define SRAM_OCI_BE_PARITY_ERR      (20)
+#define SRAM_OCI_ADDR_PARITY_ERR    (21)
+#define GPE0_HALTED                 (22)
+#define GPE1_HALTED                 (23)
+#define GPE2_HALTED                 (24)
+#define GPE3_HALTED                 (25)
+#define EXT_TRAP                    (26)
+#define PPC405_CORE_RESET           (27)
+#define PPC405_CHIP_RESET           (28)
+#define PPC405_SYS_RESET            (29)
+#define PPC405_WAIT_STATE           (30)
+#define PPC405_DBGSTOPACK           (31)
+#define OCB_DB_OCI_TIMEOUT          (32)
+#define OCB_DB_OCI_RDATA_PARITY     (33)
+#define OCB_DB_OCI_SLVERR           (34)
+#define OCB_PIB_ADDR_PARITY_ERR     (35)
+#define OCB_DB_PIB_DATA_PARITY_ERR  (36)
+#define OCB_IDC0_ERR                (37)
+#define OCB_IDC1_ERR                (38)
+#define OCB_IDC2_ERR                (39)
+#define OCB_IDC3_ERR                (40)
+#define SRT_FSM_ERR                 (41)
+#define JTAGACC_ERR                 (42)
+#define SPARE_ERR_38                (43)
+#define C405_ECC_UE                 (44)
+#define C405_ECC_CE                 (45)
+#define C405_OCI_MC_CHK             (46)
+#define SRAM_SPARE_DIRERR0          (47)
+#define SRAM_SPARE_DIRERR1          (48)
+#define SRAM_SPARE_DIRERR2          (49)
+#define SRAM_SPARE_DIRERR3          (50)
+#define GPE0_OCISLV_ERR             (51)
+#define GPE1_OCISLV_ERR             (52)
+#define GPE2_OCISLV_ERR             (53)
+#define GPE3_OCISLV_ERR             (54)
+#define C405ICU_M_TIMEOUT           (55)
+#define C405DCU_M_TIMEOUT           (56)
+#define OCC_CMPLX_FAULT             (57)
+#define OCC_CMPLX_NOTIFY            (58)
+#define SPARE_59                    (59)
+#define SPARE_60                    (60)
+#define SPARE_61                    (61)
+#define FIR_PARITY_ERR_DUP          (62)
+#define FIR_PARITY_ERR              (63)
+
+#define OCB_OCI_OCBSHCS0_PUSH_FULL   (0)
+#define OCB_OCI_OCBSHCS0_PUSH_ENABLE (31)
+
+#define OCB_PIB_OCBCSR0_OCB_STREAM_MODE (4)
+#define OCB_PIB_OCBCSR0_OCB_STREAM_TYPE (5)
+
+#define MASK_WOR_INCR (5)
+
+#define PU_PBABAR0 (0x05012B00)
+#define PU_PBABAR1 (0x05012B01)
+#define PU_PBABAR2 (0x05012B02)
+#define PU_PBABAR3 (0x05012B03)
+
+#define PU_OCB_PIB_OCBCSR0_OR (0x0006D013)
+#define PU_OCB_PIB_OCBCSR1_OR (0x0006D033)
+#define PU_OCB_PIB_OCBCSR2_OR (0x0006D053)
+#define PU_OCB_PIB_OCBCSR3_OR (0x0006D073)
+
+#define PU_OCB_PIB_OCBAR0 (0x0006D010)
+#define PU_OCB_PIB_OCBDR0 (0x0006D015)
+#define PU_OCB_PIB_OCBCSR0_RO (0x0006D011)
+#define PU_OCB_OCI_OCBSHCS0_SCOM (0x0006C204)
+
+#define OCC_405_SRAM_ADDRESS (0xFFF40000)
+#define OCC_OFFSET_MAIN_EP (0x6C)
+
+#define OCB_OITR0 (0xc0060040)
+#define OCB_OIEPR0 (0xc0060060)
+
+#define OCC_BRANCH_INSTR (0x4B00000200000000)
+#define BRANCH_ADDR_MASK (0x00FFFFFC)
+
+#define OCC_OFFSET_LENGTH (0x48)
+#define OCC_OFFSET_FREQ (0x94)
+#define OCC_OFFSET_IPL_FLAG (0x92)
+#define OCC_OFFSET_GPE0_LENGTH (0x64)
+#define OCC_OFFSET_GPE1_LENGTH (0x68)
+#define OCC_MODIFIED_SECTION_SIZE ((OCC_OFFSET_LENGTH) + (OCC_OFFSET_FREQ))
+#define OCC_LENGTH (0x120000)
+
+#define OCC_GPE0_SRAM_ADDRESS (0xFFF01000)
+#define OCC_GPE1_SRAM_ADDRESS (0xFFF10000)
+
+#define PU_SRAM_SRBV3_SCOM (0x0006A007)
+
+#define PU_SPIMPSS_ADC_CTRL_REG0 (0x00070000)
+#define PU_SPIPSS_ADC_CTRL_REG1 (0x00070001)
+#define PU_SPIPSS_ADC_CTRL_REG2 (0x00070002)
+#define PU_SPIPSS_ADC_WDATA_REG (0x00070010)
+
+#define PU_SPIPSS_P2S_CTRL_REG0 (0x00070040)
+#define PU_SPIPSS_P2S_CTRL_REG1 (0x00070041)
+#define PU_SPIPSS_P2S_CTRL_REG2 (0x00070042)
+#define PU_SPIPSS_P2S_WDATA_REG (0x00070050)
+
+#define PU_SPIPSS_100NS_REG (0x00070028)
+
+
+extern void mount_part_from_pnor(const char *part_name,
+				 struct mmap_helper_region_device *mdev);
+
+const uint64_t PBA_BARs[4] =
+{
+    PU_PBABAR0,
+    PU_PBABAR1,
+    PU_PBABAR2,
+    PU_PBABAR3
+};

src/include/cpu/power/occ.h

@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CPU_PPC64_OCC_H
+#define CPU_PPC64_OCC_H
+
+#include <cpu/power/scom.h>
+
+#define OCC_405_SRAM_ADDRESS (0xFFF40000)
+#define OCC_OFFSET_MAIN_EP (0x6C)
+#define OCC_BRANCH_INSTR (0x4B00000200000000)
+#define BRANCH_ADDR_MASK (0x00FFFFFC)
+
+#define OCB_PIB_OCBCSR0_OCB_STREAM_MODE (4)
+#define OCB_PIB_OCBCSR0_OCB_STREAM_TYPE (5)
+
+#define OCB_OCI_OCBSHCS0_PUSH_ENABLE (31)
+#define OCB_OCI_OCBSHCS0_PUSH_FULL   (0)
+
+#define PU_OCB_PIB_OCBCSR0_RO (0x0006D011)
+#define PU_OCB_OCI_OCBSHCS0_SCOM (0x0006C204)
+#define PU_OCB_PIB_OCBDR0 (0x0006D015)
+
+#define PU_OCB_PIB_OCBCSR0_OR (0x0006D013)
+#define PU_OCB_PIB_OCBCSR1_OR (0x0006D033)
+#define PU_OCB_PIB_OCBCSR2_OR (0x0006D053)
+#define PU_OCB_PIB_OCBCSR3_OR (0x0006D073)
+
+#define PU_OCB_PIB_OCBCSR0_CLEAR (0x0006D012)
+#define PU_OCB_PIB_OCBCSR1_CLEAR (0x0006D032)
+#define PU_OCB_PIB_OCBCSR2_CLEAR (0x0006D052)
+#define PU_OCB_PIB_OCBCSR3_CLEAR (0x0006D072)
+
+#define PU_OCB_PIB_OCBAR0 (0x0006D010)
+#define PU_OCB_PIB_OCBAR1 (0x0006D030)
+#define PU_OCB_PIB_OCBAR2 (0x0006D050)
+#define PU_OCB_PIB_OCBAR3 (0x0006D070)
+
+#define EX_PPM_SPWKUP_OCC (0x200F010C)
+
+#define NUMBER_OF_EX_CHIPLETS (6)
+const chiplet_id_t EX_CHIPLETS[NUMBER_OF_EX_CHIPLETS] =
+{
+    EP00_CHIPLET_ID,
+	EP01_CHIPLET_ID,
+	EP02_CHIPLET_ID,
+	EP03_CHIPLET_ID,
+	EP04_CHIPLET_ID,
+	EP05_CHIPLET_ID
+};
+
+const uint64_t OCBARn[4] =
+{
+    PU_OCB_PIB_OCBAR0,
+    PU_OCB_PIB_OCBAR1,
+    PU_OCB_PIB_OCBAR2,
+    PU_OCB_PIB_OCBAR3
+};
+
+const uint64_t OCBCSRn_CLEAR[4] =
+{
+    PU_OCB_PIB_OCBCSR0_CLEAR,
+    PU_OCB_PIB_OCBCSR1_CLEAR,
+    PU_OCB_PIB_OCBCSR2_CLEAR,
+    PU_OCB_PIB_OCBCSR3_CLEAR
+};
+
+const uint64_t OCBCSRn_OR[4] =
+{
+    PU_OCB_PIB_OCBCSR0_OR,
+    PU_OCB_PIB_OCBCSR1_OR,
+    PU_OCB_PIB_OCBCSR2_OR,
+    PU_OCB_PIB_OCBCSR3_OR
+};
+
+void writeOCCSRAM(
+    const uint32_t address,
+    uint64_t * buffer,
+    size_t data_length);
+void readOCCSRAM(
+    const uint32_t address,
+    uint64_t * buffer,
+    size_t data_length);
+uint64_t makeStart405Instruction(void);
+void clear_occ_special_wakeups(void);
+
+#endif /* CPU_PPC64_OCC_H */

src/include/cpu/power/scom.h

@@ -217,5 +217,12 @@ static inline void scom_or_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint
 	scom_and_or_for_chiplet(chiplet, addr, ~0, or);
 }
 
+static inline uint8_t get_dd(void)
+{
+	uint64_t val = read_scom(0xF000F);
+	val = ((val >> 52) & 0x0F) | ((val >> 56) & 0xF0);
+	return (uint8_t) val;
+}
+
 #endif /* __ASSEMBLER__ */
 #endif /* CPU_PPC64_SCOM_H */

src/include/cpu/power/spr.h

@@ -7,21 +7,29 @@
 #define SPR_DEC_IMPLEMENTED_BITS		56
 #define SPR_DEC_LONGEST_TIME			((1ull << (SPR_DEC_IMPLEMENTED_BITS - 1)) - 1)
 
-#define SPR_TB					0x10C
-
-#define SPR_PVR					0x11F
-#define SPR_PVR_REV_MASK			(PPC_BITMASK(52, 55) | PPC_BITMASK(60, 63))
-#define SPR_PVR_REV(maj, min)			(PPC_SHIFT((maj), 55) | PPC_SHIFT((min), 63))
+#define SPR_SRR0				0x2A
+#define SPR_SRR1				0x2B
 
+#define SPR_DAWR				0xB4
+#define SPR_CIABR				0xBB
+#define SPR_DAWRX				0xBC
+#define SPR_TB					0x10C
+#define SPR_HSPRG0				0x130
 #define SPR_HDEC				0x136
 #define SPR_HRMOR				0x139
 
 #define SPR_LPCR				0x13E
+#define SPR_LPCR_HVEE				PPC_BIT(17)
 #define SPR_LPCR_LD				PPC_BIT(46)
+#define SPR_LPCR_EEE				PPC_BIT(49)
+#define SPR_LPCR_DEE				PPC_BIT(50)
+#define SPR_LPCR_OEE				PPC_BIT(51)
 #define SPR_LPCR_HEIC				PPC_BIT(59)
+#define SPR_LPCR_HVICE				PPC_BIT(62)
 #define SPR_LPCR_HDICE				PPC_BIT(63)
 
 #define SPR_HMER				0x150
+#define SPR_HMEER				0x151
 /* Bits in HMER/HMEER */
 #define SPR_HMER_MALFUNCTION_ALERT		PPC_BIT(0)
 #define SPR_HMER_PROC_RECV_DONE			PPC_BIT(2)
@@ -39,6 +47,10 @@
 #define SPR_HMER_XSCOM_STATUS			PPC_BITMASK(21,23)
 #define SPR_HMER_XSCOM_OCCUPIED			PPC_BIT(23)
 
+#define SPR_PTCR				0x1D0
+#define SPR_PSSCR				0x357
+#define SPR_PMCR				0x374
+
 #ifndef __ASSEMBLER__
 #include <types.h>
 
@@ -77,10 +89,5 @@ static inline void write_msr(uint64_t val)
 	asm volatile("mtmsrd %0" :: "r"(val) : "memory");
 }
 
-static inline uint64_t pvr_revision(void)
-{
-	return read_spr(SPR_PVR) & SPR_PVR_REV_MASK;
-}
-
 #endif /* __ASSEMBLER__ */
 #endif /* CPU_PPC64_SPR_H */

src/soc/ibm/power9/Makefile.inc

@@ -4,9 +4,9 @@ ifeq ($(CONFIG_CPU_IBM_POWER9),y)
 
 bootblock-y += bootblock.c
 bootblock-y += rom_media.c
-romstage-y += rom_media.c
-romstage-y += romstage.c
-romstage-y += vpd.c
+romstage-y += ccs.c
+romstage-y += i2c.c
+romstage-y += istep_6_11.c
 romstage-y += istep_13_2.c
 romstage-y += istep_13_3.c
 romstage-y += istep_13_4.c
@@ -20,10 +20,13 @@ romstage-y += istep_14_1.c
 romstage-y += istep_14_2.c
 romstage-y += istep_14_3.c
 romstage-y += istep_14_5.c
-romstage-y += i2c.c
-romstage-y += ccs.c
+romstage-y += occ.c
+romstage-y += rom_media.c
+romstage-y += romstage.c
 romstage-y += timer.c
+romstage-y += vpd.c
 ramstage-y += chip.c
+ramstage-y += homer.c
 ramstage-y += rom_media.c
 ramstage-y += timer.c
 

src/soc/ibm/power9/chip.c

@@ -3,7 +3,9 @@
 #include <device/device.h>
 #include <fit.h>
 #include <cpu/power/istep_13.h>
+
 #include "istep_13_scom.h"
+#include "chip.h"
 
 static int dt_platform_fixup(struct device_tree_fixup *fixup,
 			      struct device_tree *tree)
@@ -42,6 +44,7 @@ static inline unsigned long size_k(uint64_t reg)
 static void enable_soc_dev(struct device *dev)
 {
 	int mcs_i, idx = 0;
+	unsigned long reserved_size, top = 0;
 
 	for (mcs_i = 0; mcs_i < MCS_PER_PROC; mcs_i++) {
 		uint64_t reg;
@@ -50,15 +53,31 @@ static void enable_soc_dev(struct device *dev)
 		/* These registers are undocumented, see istep 14.5. */
 		/* MCS_MCFGP */
 		reg = read_scom_for_chiplet(nest, 0x0501080A);
-		if (reg & PPC_BIT(0))
+		if (reg & PPC_BIT(0)) {
 			ram_resource(dev, idx++, base_k(reg), size_k(reg));
+			if (base_k(reg) + size_k(reg) > top)
+				top = base_k(reg) + size_k(reg);
+		}
 
 		/* MCS_MCFGPM */
 		reg = read_scom_for_chiplet(nest, 0x0501080C);
-		if (reg & PPC_BIT(0))
+		if (reg & PPC_BIT(0)) {
 			ram_resource(dev, idx++, base_k(reg), size_k(reg));
+			if (base_k(reg) + size_k(reg) > top)
+				top = base_k(reg) + size_k(reg);
+		}
 	}
 
+	/*
+	 * Reserve top 8M (OCC common area) + 4M (HOMER).
+	 *
+	 * TODO: 8M + (4M per CPU), hostboot reserves always 8M + 8 * 4M.
+	 */
+	reserved_size = 8*1024 + 4*1024 *8 /* * num_of_cpus */;
+	top -= reserved_size;
+	reserved_ram_resource(dev, idx++, top, reserved_size);
+	build_homer_image((void *)(top * 1024));
+
 	if (CONFIG(PAYLOAD_FIT_SUPPORT)) {
 		struct device_tree_fixup *dt_fixup;
 

src/soc/ibm/power9/chip.h

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_IBM_POWER9_CHIP_H
+#define __SOC_IBM_POWER9_CHIP_H
+
+struct soc_ibm_power9_config {
+};
+
+void build_homer_image(void *homer_bar);
+
+#endif /* __SOC_CAVIUM_CN81XX_CHIP_H */