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Inline assembly integer formatter implicitly converts unsigned integer to signed, then sign-extends to power of 2 #21431

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Validark opened this issue Sep 16, 2024 · 1 comment
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backend-llvm The LLVM backend outputs an LLVM IR Module. bug Observed behavior contradicts documented or intended behavior miscompilation The compiler reports success but produces semantically incorrect code.
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@Validark
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Validark commented Sep 16, 2024

Zig Version

0.14.0-dev.1417+242d268a0

Steps to Reproduce and Observed Behavior

Godbolt link

This code:

fn valignq(a: @Vector(64, u8), b: @Vector(64, u8), comptime imm: u6) @Vector(64, u8) {
    return asm (
        \\valignq %[imm], %[b], %[a], %[out]
        : [out] "=v" (-> @Vector(64, u8)),
        : [a] "v" (a),
          [b] "v" (b),
          [imm] "n" (imm),
    );
}

export fn valignq_ext(a: @Vector(64, u8), b: @Vector(64, u8)) @Vector(64, u8) {
    return valignq(a, b, 32);
}

Results in this assembly:

valignq_ext:
        valignq zmm0, zmm0, zmm1, 224
        ret

What I assume is happening here is described in the title. 32 as a u6 is 0b100000, but this gets turned into an i6, then sign-extended to an i8. So we end up with 0b11100000, which is 224 as a u8.

This can be worked around by wrapping imm in @as(u8, imm):

fn valignq(a: @Vector(64, u8), b: @Vector(64, u8), comptime imm: u6) @Vector(64, u8) {
    return asm (
        \\valignq %[imm], %[b], %[a], %[out]
        : [out] "=v" (-> @Vector(64, u8)),
        : [a] "v" (a),
          [b] "v" (b),
          [imm] "n" (@as(u8, imm)),
    );
}

It would be nice if the language did this automatically or if there was a helpful compiler error.

Expected Behavior

valignq_ext:
        valignq zmm0, zmm0, zmm1, 32
        ret
@Validark Validark added the bug Observed behavior contradicts documented or intended behavior label Sep 16, 2024
@Vexu Vexu added backend-llvm The LLVM backend outputs an LLVM IR Module. miscompilation The compiler reports success but produces semantically incorrect code. labels Sep 16, 2024
@Vexu Vexu added this to the 0.14.0 milestone Sep 16, 2024
@Vexu
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Vexu commented Sep 16, 2024

Simplified version:

export fn valignq_ext() void {
    const number: u6 = 32;
    asm volatile (
        \\mov %[number], %%rax
        : : [number] "n" (number)
    );
}
$ zig build-obj a.zig -fstrip
$ llvm-objdump -d a.o
a.o:    file format elf64-x86-64

Disassembly of section .text:

0000000000000000 <valignq_ext>:
       0: 55                            pushq   %rbp
       1: 48 89 e5                      movq    %rsp, %rbp
       4: 48 c7 c0 e0 ff ff ff          movq    $-0x20, %rax
       b: 5d                            popq    %rbp
       c: c3                            retq
$ zig build-obj a.zig -fstrip -fno-llvm -fno-lld
$ llvm-objdump -d a.o
a.o:    file format elf64-x86-64

Disassembly of section .text:

0000000000000000 <valignq_ext>:
       0: 55                            pushq   %rbp
       1: 48 89 e5                      movq    %rsp, %rbp
       4: 48 c7 c0 20 00 00 00          movq    $0x20, %rax
       b: e9 00 00 00 00                jmp     0x10 <valignq_ext+0x10>
      10: 5d                            popq    %rbp
      11: c3                            retq

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Labels
backend-llvm The LLVM backend outputs an LLVM IR Module. bug Observed behavior contradicts documented or intended behavior miscompilation The compiler reports success but produces semantically incorrect code.
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