Skip to content

Commit e7cc834

Browse files
kartbenkartben
committed
dts: stm32: Streamline device tree binding descriptions
Ensure consistent (and concise) short descriptions of all the st,*.yaml bindings Signed-off-by: Benjamin Cabé <[email protected]>
1 parent 14f382b commit e7cc834

File tree

90 files changed

+130
-92
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

90 files changed

+130
-92
lines changed

‎dts/bindings/adc/st,stm32-adc.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# Copyright (c) 2018, Song Qiang <[email protected]>
33
# SPDX-License-Identifier: Apache-2.0
44

5-
description: ST STM32 family ADC
5+
description: STM32 ADC
66

77
compatible: "st,stm32-adc"
88

‎dts/bindings/adc/st,stm32f1-adc.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,8 @@
33
# SPDX-License-Identifier: Apache-2.0
44

55
description: |
6-
ST STM32F1 family ADC
6+
STM32F1 ADC
7+
78
This compatible stands for all ADC blocks similar to the one on STM32F1,
89
like STM32F37x.
910
Remove the st,adc-clock-source and st,adc-prescaler property.

‎dts/bindings/adc/st,stm32f4-adc.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,8 @@
33
# SPDX-License-Identifier: Apache-2.0
44

55
description: |
6-
ST STM32F4 family ADC
6+
STM32F4 ADC
7+
78
This compatible stands for all ADC blocks similar to the one on STM32F4,
89
like F2, F7 or L1.
910

‎dts/bindings/adc/st,stm32n6-adc.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,8 @@
33
# SPDX-License-Identifier: Apache-2.0
44

55
description: |
6-
ST STM32N6 ADC
6+
STM32N6 ADC
7+
78
This compatible stands for STM32N6 ADC.
89
910
compatible: "st,stm32n6-adc"

‎dts/bindings/adc/st,stm32wb0-adc.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# SPDX-License-Identifier: Apache-2.0
22

3-
description: STM32WB0 series Analog-to-Digital Converter
3+
description: STM32WB0 Analog-to-Digital Converter
44

55
compatible: "st,stm32wb0-adc"
66

‎dts/bindings/can/st,stm32-fdcan.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
description: ST STM32 FDCAN CAN FD controller
1+
description: STM32 FDCAN CAN FD controller
22

33
compatible: "st,stm32-fdcan"
44

‎dts/bindings/can/st,stm32h7-fdcan.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
description: ST STM32H7 series FDCAN CAN FD controller
1+
description: STM32H7 series FDCAN CAN FD controller
22

33
compatible: "st,stm32h7-fdcan"
44

‎dts/bindings/clock/st,stm32-clock-mux.yaml

+1
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33

44
description: |
55
STM32 Clock multiplexer
6+
67
Describes a clock multiplexer, such as per_ck on STM32H7 or
78
CLK48 on STM32WB.
89
The only property of this node is to select a clock input.

‎dts/bindings/clock/st,stm32-rcc.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32 Reset and Clock controller node.
5+
STM32 RCC (Reset and Clock controller).
6+
67
This node is in charge of system clock ('SYSCLK') source selection and controlling
78
clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
89

‎dts/bindings/clock/st,stm32c0-hsi-clock.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32 HSI Clock node description for STM32C0 devices
5+
STM32C0 HSI Clock.
6+
67
On STM32C0, HSI is a 48MHz fixed clock.
78
89
It also produces a HSISYS secondary clk which can be used as system clock

‎dts/bindings/clock/st,stm32f0-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
Main PLL node binding for STM32F0 and STM32F3 devices.
5+
STM32F0/F3 Main PLL.
66
77
Takes one of clk_hse or clk_hsi as input clock.
88

‎dts/bindings/clock/st,stm32f0-rcc.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32F0 and G0 Reset and Clock controller node.
5+
STM32F0/G0 RCC (Reset and Clock controller).
6+
67
For more description confere st,stm32-rcc.yaml
78
89
compatible: "st,stm32f0-rcc"

‎dts/bindings/clock/st,stm32f1-clock-mco.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
compatible: "st,stm32f1-clock-mco"
88

99
description: |
10-
STM32 F1 series Microcontroller Clock Output (MCO)
10+
STM32F1 Microcontroller Clock Output (MCO)
1111
1212
The STM32F1 MCO is similar to other series but has no configurable
1313
prescaler before the output. However, note that certain inputs of

‎dts/bindings/clock/st,stm32f1-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
5+
STM32F1 Main PLL for low-, medium-, high- and XL-density devices.
66
77
Takes one of 'clk_hse', 'clk_hse / 2' (when 'xtpre' is set) or 'clk_hsi / 2'
88
as input clock.

‎dts/bindings/clock/st,stm32f1-rcc.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32F1 and STM32F37x Reset and Clock controller node.
5+
STM32F1/F3/7x RCC (Reset and Clock controller).
6+
67
Adds the ADC prescaler to the standard generic STM32 RCC.
78
For more description confere st,stm32-rcc.yaml
89

‎dts/bindings/clock/st,stm32f100-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
Main PLL node binding for STM32F100 devices
5+
STM32F100 Main PLL.
66
77
Takes one of clk_hse or clk_hsi as input clock.
88
When clk_hsi is used a fixed prescaler is applied. When input clock is hse or

‎dts/bindings/clock/st,stm32f105-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
Main PLL node binding for Connectivity line devices (STM32F105/STM32F107)
5+
STM32F105/F107 Main PLL.
66
77
Takes one of clk_hse, pll2 or clk_hsi as input clock.
88
When clk_hsi is used a fixed prescaler is applied. When input clock is hse or

‎dts/bindings/clock/st,stm32f105-pll2-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
PLL2 node binding for Connectivity line devices (STM32F105/STM32F107)
5+
STM32F105/F107 PLL2.
66
77
Takes clk_hse as input clock, using prediv as prescaler.
88

‎dts/bindings/clock/st,stm32f2-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32F2 Main PLL node binding:
5+
STM32F2 Main PLL.
66
77
Takes one of clk_hse or clk_hsi as input clock.
88

‎dts/bindings/clock/st,stm32f3-rcc.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32F3 Reset and Clock controller node.
5+
STM32F3 RCC (Reset and Clock controller).
6+
67
Adds the STM32F3 ADC prescaler to the standard generic STM32 RCC.
78
For more description confere st,stm32-rcc.yaml
89

‎dts/bindings/clock/st,stm32f4-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32F4 Main PLL node binding:
5+
STM32F4 Main PLL.
66
77
Takes one of clk_hse or clk_hsi as input clock, with an
88
input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock

‎dts/bindings/clock/st,stm32f4-plli2s-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32F4 PLL I2S node binding:
5+
STM32F4 PLL I2S.
66
77
Takes same input as Main PLL. PLLM factor and PLL source are common with Main PLL
88

‎dts/bindings/clock/st,stm32f411-plli2s-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32F411 PLL I2S node binding:
5+
STM32F411 PLL I2S.
66
77
Fully configurable I2S dedicated PLL.
88

‎dts/bindings/clock/st,stm32f7-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32F7 Main PLL node binding:
5+
STM32F7 Main PLL.
66
77
Takes one of clk_hse or clk_hsi as input clock.
88

‎dts/bindings/clock/st,stm32g0-hsi-clock.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32 HSI Clock node description for STM32G0 devices
5+
STM32G0 HSI Clock.
6+
67
On STM32G0, HSI is a 16MHz fixed clock.
78
89
It also produces a HSISYS secondary clk which can be used as system clock

‎dts/bindings/clock/st,stm32g0-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
PLL node binding for STM32G0 devices
5+
STM32G0 main PLL.
66
77
It can take one of clk_hse or clk_hsi as input clock, with
88
an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input

‎dts/bindings/clock/st,stm32g4-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
PLL node binding for STM32G4 devices
5+
STM32G4 main PLL.
66
77
It can take one of clk_hse or clk_hsi as input clock, with
88
an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input

‎dts/bindings/clock/st,stm32h7-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
PLL node binding for STM32H7 devices
5+
STM32H7 main PLL.
66
77
It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
88
Only PLL1 and PLL3 are supported for now.

‎dts/bindings/clock/st,stm32h7-rcc.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32 Reset and Clock controller node for STM32H7 devices
5+
STM32H7 RCC (Reset and Clock controller).
6+
67
This node is in charge of system clock ('SYSCLK') source selection and
78
System Clock Generation.
89

‎dts/bindings/clock/st,stm32h7rs-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
PLL node binding for STM32H7RS devices
5+
STM32H7RS main PLL.
66
77
It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
88

‎dts/bindings/clock/st,stm32h7rs-rcc.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32 Reset and Clock controller node for STM32H7RS devices
5+
STM32H7RS RCC (Reset and Clock controller).
6+
67
This node is in charge of system clock ('SYSCLK') source selection and
78
System Clock Generation.
89

‎dts/bindings/clock/st,stm32l0-msi-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# Copyright (c) 2021, Linaro ltd
22
# SPDX-License-Identifier: Apache-2.0
33

4-
description: STM32L0 and STM32L1 Multi Speed Internal Clock
4+
description: STM32L0/L1 Multi Speed Internal Clock
55

66
compatible: "st,stm32l0-msi-clock"
77

‎dts/bindings/clock/st,stm32l0-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32L0 and STM32L1 Main PLL node binding:
5+
STM32L0/L1 Main PLL.
66
77
Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
88
input frequency from 2 to 24 MHz.

‎dts/bindings/clock/st,stm32l4-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
PLL node binding for STM32L4 and STM32L5 devices
5+
STM32L4/L5 main PLL.
66
77
It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
88
Only main PLL is supported for now.

‎dts/bindings/clock/st,stm32mp1-rcc.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32MP1 Reset and Clock controller node.
5+
STM32MP1 RCC (Reset and Clock controller).
6+
67
On STM32MP1 platforms, clock control configuration is performed on A9 side.
78
As a consequence, the only property to be set in devicetree node is the
89
clock-frequency (mlhclk_ck).

‎dts/bindings/clock/st,stm32n6-cpu-clock-mux.yaml

+3-1
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,11 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32N6 CPU Clock
5+
STM32N6 CPU Clock.
6+
67
Describes the STM32N6 CPU clock multiplexer. On STM32N6, this is the CPU
78
clock that feeds the SysTick.
9+
810
For instance:
911
&cpusw {
1012
clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;

‎dts/bindings/clock/st,stm32n6-ic-clock-mux.yaml

+4-2
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,10 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32N6 Divider IC multiplexer
6-
This node select a clock input and a divider.
5+
STM32N6 Divider IC multiplexer.
6+
7+
This node selects a clock input and a divider.
8+
79
For instance:
810
&ic6 {
911
pll-src = <2>;

‎dts/bindings/clock/st,stm32n6-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
PLL node binding for STM32N6 devices
5+
STM32N6 main PLL.
66
77
It can be used to describe 4 different PLLs: PLL1, PLL2, PLL3 and PLL4.
88

‎dts/bindings/clock/st,stm32n6-rcc.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32 Reset and Clock controller node for STM32N6 devices
5+
STM32N6 RCC (Reset and Clock controller).
6+
67
This node is in charge of system clock ('SYSCLK') source selection and
78
System Clock Generation.
89

‎dts/bindings/clock/st,stm32u0-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32U0 Main PLL node binding:
5+
STM32U0 Main PLL.
66
77
Takes one of clk_hse, clk_hsi or clk_msi as input clock, with
88
an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input

‎dts/bindings/clock/st,stm32u5-pll-clock.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
PLL node binding for STM32U5 devices
5+
STM32U5 PLL.
66
77
It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3.
88

‎dts/bindings/clock/st,stm32u5-rcc.yaml

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
description: |
5-
STM32U5 Reset and Clock controller node.
5+
STM32U5 RCC (Reset and Clock controller).
6+
67
For more description confere st,stm32-rcc.yaml
78
89
compatible: "st,stm32u5-rcc"

‎dts/bindings/clock/st,stm32wb-rcc.yaml

+1
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33

44
description: |
55
STM32WB Reset and Clock controller node.
6+
67
For more description confere st,stm32-rcc.yaml
78
89
compatible: "st,stm32wb-rcc"

0 commit comments

Comments
 (0)