From 8c1d89fcb3612ee585ff5b2f034ac218c623c2f9 Mon Sep 17 00:00:00 2001 From: Fabrice DJIATSA Date: Thu, 17 Apr 2025 09:26:05 +0200 Subject: [PATCH 1/3] stm32cube: stm32h7rsxx: soc: update h7 soc files sync soc files with the correct h7rs cube repository history. Signed-off-by: Fabrice DJIATSA --- stm32cube/stm32h7rsxx/soc/stm32h7r3xx.h | 8 +------- stm32cube/stm32h7rsxx/soc/stm32h7r7xx.h | 8 +------- stm32cube/stm32h7rsxx/soc/stm32h7s3xx.h | 8 +------- stm32cube/stm32h7rsxx/soc/stm32h7s7xx.h | 8 +------- 4 files changed, 4 insertions(+), 28 deletions(-) diff --git a/stm32cube/stm32h7rsxx/soc/stm32h7r3xx.h b/stm32cube/stm32h7rsxx/soc/stm32h7r3xx.h index d39bb6541..e7201a147 100644 --- a/stm32cube/stm32h7rsxx/soc/stm32h7r3xx.h +++ b/stm32cube/stm32h7rsxx/soc/stm32h7r3xx.h @@ -2108,7 +2108,6 @@ typedef struct #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) #define XSPI1_R_BASE (AHB5PERIPH_BASE + 0x5000UL) -#define DLYB_XSPI1_BASE (AHB5PERIPH_BASE + 0x6000UL) #define SDMMC1_BASE (AHB5PERIPH_BASE + 0x7000UL) #define DLYB_SDMMC1_BASE (AHB5PERIPH_BASE + 0x8000UL) #define RAMECC1_BASE (AHB5PERIPH_BASE + 0x9000UL) @@ -2118,7 +2117,6 @@ typedef struct #define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x80UL) #define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0xA0UL) #define XSPI2_R_BASE (AHB5PERIPH_BASE + 0xA000UL) -#define DLYB_XSPI2_BASE (AHB5PERIPH_BASE + 0xB000UL) #define XSPIM_BASE (AHB5PERIPH_BASE + 0xB400UL) #define GFXMMU_BASE (AHB5PERIPH_BASE + 0x010000UL) @@ -2379,8 +2377,6 @@ typedef struct #define DCMIPP ((DCMIPP_TypeDef *) DCMIPP_BASE) #define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) -#define DLYB_XSPI1 ((DLYB_TypeDef *) DLYB_XSPI1_BASE) -#define DLYB_XSPI2 ((DLYB_TypeDef *) DLYB_XSPI2_BASE) #define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) #define DTS ((DTS_TypeDef *) DTS_BASE) #define ETH ((ETH_TypeDef *)ETH_BASE) @@ -22634,9 +22630,7 @@ typedef struct #define IS_DCMIPP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMIPP) /******************************* DLYB Instances *******************************/ -#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_XSPI1) || \ - ((INSTANCE) == DLYB_XSPI2) || \ - ((INSTANCE) == DLYB_SDMMC1) || \ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \ ((INSTANCE) == DLYB_SDMMC2)) /******************************** DMA Instances *******************************/ diff --git a/stm32cube/stm32h7rsxx/soc/stm32h7r7xx.h b/stm32cube/stm32h7rsxx/soc/stm32h7r7xx.h index 422f869e0..e0bc9abf9 100644 --- a/stm32cube/stm32h7rsxx/soc/stm32h7r7xx.h +++ b/stm32cube/stm32h7rsxx/soc/stm32h7r7xx.h @@ -2178,7 +2178,6 @@ typedef struct #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) #define XSPI1_R_BASE (AHB5PERIPH_BASE + 0x5000UL) -#define DLYB_XSPI1_BASE (AHB5PERIPH_BASE + 0x6000UL) #define SDMMC1_BASE (AHB5PERIPH_BASE + 0x7000UL) #define DLYB_SDMMC1_BASE (AHB5PERIPH_BASE + 0x8000UL) #define RAMECC1_BASE (AHB5PERIPH_BASE + 0x9000UL) @@ -2188,7 +2187,6 @@ typedef struct #define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x80UL) #define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0xA0UL) #define XSPI2_R_BASE (AHB5PERIPH_BASE + 0xA000UL) -#define DLYB_XSPI2_BASE (AHB5PERIPH_BASE + 0xB000UL) #define XSPIM_BASE (AHB5PERIPH_BASE + 0xB400UL) #define GFXMMU_BASE (AHB5PERIPH_BASE + 0x010000UL) #define GPU2D_BASE (AHB5PERIPH_BASE + 0x014000UL) @@ -2451,8 +2449,6 @@ typedef struct #define DCMIPP ((DCMIPP_TypeDef *) DCMIPP_BASE) #define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) -#define DLYB_XSPI1 ((DLYB_TypeDef *) DLYB_XSPI1_BASE) -#define DLYB_XSPI2 ((DLYB_TypeDef *) DLYB_XSPI2_BASE) #define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) #define DTS ((DTS_TypeDef *) DTS_BASE) #define ETH ((ETH_TypeDef *)ETH_BASE) @@ -23064,9 +23060,7 @@ typedef struct #define IS_DCMIPP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMIPP) /******************************* DLYB Instances *******************************/ -#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_XSPI1) || \ - ((INSTANCE) == DLYB_XSPI2) || \ - ((INSTANCE) == DLYB_SDMMC1) || \ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \ ((INSTANCE) == DLYB_SDMMC2)) /******************************** DMA Instances *******************************/ diff --git a/stm32cube/stm32h7rsxx/soc/stm32h7s3xx.h b/stm32cube/stm32h7rsxx/soc/stm32h7s3xx.h index f675ff138..b7a45d27f 100644 --- a/stm32cube/stm32h7rsxx/soc/stm32h7s3xx.h +++ b/stm32cube/stm32h7rsxx/soc/stm32h7s3xx.h @@ -2238,7 +2238,6 @@ typedef struct #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) #define XSPI1_R_BASE (AHB5PERIPH_BASE + 0x5000UL) -#define DLYB_XSPI1_BASE (AHB5PERIPH_BASE + 0x6000UL) #define SDMMC1_BASE (AHB5PERIPH_BASE + 0x7000UL) #define DLYB_SDMMC1_BASE (AHB5PERIPH_BASE + 0x8000UL) #define RAMECC1_BASE (AHB5PERIPH_BASE + 0x9000UL) @@ -2248,7 +2247,6 @@ typedef struct #define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x80UL) #define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0xA0UL) #define XSPI2_R_BASE (AHB5PERIPH_BASE + 0xA000UL) -#define DLYB_XSPI2_BASE (AHB5PERIPH_BASE + 0xB000UL) #define XSPIM_BASE (AHB5PERIPH_BASE + 0xB400UL) #define MCE1_BASE (AHB5PERIPH_BASE + 0xB800UL) #define MCE1_REGION1_BASE (MCE1_BASE + 0x040UL) @@ -2527,8 +2525,6 @@ typedef struct #define DCMIPP ((DCMIPP_TypeDef *) DCMIPP_BASE) #define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) -#define DLYB_XSPI1 ((DLYB_TypeDef *) DLYB_XSPI1_BASE) -#define DLYB_XSPI2 ((DLYB_TypeDef *) DLYB_XSPI2_BASE) #define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) #define DTS ((DTS_TypeDef *) DTS_BASE) #define ETH ((ETH_TypeDef *)ETH_BASE) @@ -23517,9 +23513,7 @@ typedef struct #define IS_DCMIPP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMIPP) /******************************* DLYB Instances *******************************/ -#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_XSPI1) || \ - ((INSTANCE) == DLYB_XSPI2) || \ - ((INSTANCE) == DLYB_SDMMC1) || \ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \ ((INSTANCE) == DLYB_SDMMC2)) /******************************** DMA Instances *******************************/ diff --git a/stm32cube/stm32h7rsxx/soc/stm32h7s7xx.h b/stm32cube/stm32h7rsxx/soc/stm32h7s7xx.h index d3435641c..bb5c7c454 100644 --- a/stm32cube/stm32h7rsxx/soc/stm32h7s7xx.h +++ b/stm32cube/stm32h7rsxx/soc/stm32h7s7xx.h @@ -2308,7 +2308,6 @@ typedef struct #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) #define XSPI1_R_BASE (AHB5PERIPH_BASE + 0x5000UL) -#define DLYB_XSPI1_BASE (AHB5PERIPH_BASE + 0x6000UL) #define SDMMC1_BASE (AHB5PERIPH_BASE + 0x7000UL) #define DLYB_SDMMC1_BASE (AHB5PERIPH_BASE + 0x8000UL) #define RAMECC1_BASE (AHB5PERIPH_BASE + 0x9000UL) @@ -2318,7 +2317,6 @@ typedef struct #define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x80UL) #define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0xA0UL) #define XSPI2_R_BASE (AHB5PERIPH_BASE + 0xA000UL) -#define DLYB_XSPI2_BASE (AHB5PERIPH_BASE + 0xB000UL) #define XSPIM_BASE (AHB5PERIPH_BASE + 0xB400UL) #define MCE1_BASE (AHB5PERIPH_BASE + 0xB800UL) #define MCE1_REGION1_BASE (MCE1_BASE + 0x040UL) @@ -2599,8 +2597,6 @@ typedef struct #define DCMIPP ((DCMIPP_TypeDef *) DCMIPP_BASE) #define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) -#define DLYB_XSPI1 ((DLYB_TypeDef *) DLYB_XSPI1_BASE) -#define DLYB_XSPI2 ((DLYB_TypeDef *) DLYB_XSPI2_BASE) #define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) #define DTS ((DTS_TypeDef *) DTS_BASE) #define ETH ((ETH_TypeDef *)ETH_BASE) @@ -23947,9 +23943,7 @@ typedef struct #define IS_DCMIPP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMIPP) /******************************* DLYB Instances *******************************/ -#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_XSPI1) || \ - ((INSTANCE) == DLYB_XSPI2) || \ - ((INSTANCE) == DLYB_SDMMC1) || \ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \ ((INSTANCE) == DLYB_SDMMC2)) /******************************** DMA Instances *******************************/ From 32aebe53ed6b99143507b238d7ef5eb007f038e5 Mon Sep 17 00:00:00 2001 From: Fabrice DJIATSA Date: Thu, 17 Apr 2025 10:04:03 +0200 Subject: [PATCH 2/3] stm32cube: stm32h7rsxx: drivers: include: update hal-ll header synchronize hal-ll header files with correct h7rs cube repository history. Signed-off-by: Fabrice DJIATSA --- .../drivers/include/Legacy/stm32_hal_legacy.h | 14 ++++++- .../drivers/include/stm32h7rsxx_hal_cortex.h | 2 +- .../drivers/include/stm32h7rsxx_hal_def.h | 4 ++ .../include/stm32h7rsxx_hal_flash_ex.h | 4 +- .../drivers/include/stm32h7rsxx_hal_mdios.h | 2 +- .../drivers/include/stm32h7rsxx_hal_rcc.h | 4 -- .../drivers/include/stm32h7rsxx_hal_rcc_ex.h | 6 +-- .../drivers/include/stm32h7rsxx_hal_rng_ex.h | 39 ++++++++++--------- .../drivers/include/stm32h7rsxx_hal_sdio.h | 15 ++++--- .../include/stm32h7rsxx_hal_usart_ex.h | 1 + .../drivers/include/stm32h7rsxx_ll_dlyb.h | 8 ++-- .../drivers/include/stm32h7rsxx_ll_rcc.h | 4 +- .../drivers/include/stm32h7rsxx_ll_rng.h | 13 ++++--- 13 files changed, 67 insertions(+), 49 deletions(-) diff --git a/stm32cube/stm32h7rsxx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32h7rsxx/drivers/include/Legacy/stm32_hal_legacy.h index 39b76405b..e41f25afc 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/Legacy/stm32_hal_legacy.h +++ b/stm32cube/stm32h7rsxx/drivers/include/Legacy/stm32_hal_legacy.h @@ -554,6 +554,16 @@ extern "C" { #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ /** * @} @@ -3792,10 +3802,10 @@ extern "C" { #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 - +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 - +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 diff --git a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_cortex.h b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_cortex.h index dc90934d3..6dee7e4d9 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_cortex.h +++ b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_cortex.h @@ -388,7 +388,7 @@ void HAL_CORTEX_ClearEvent(void); #define IS_MPU_SUB_REGION_DISABLE(__SUBREGION__) ((__SUBREGION__) < (uint16_t)0x00FFU) -#define IS_MPU_ADDRESS_MULTIPLE_SIZE(__ADDRESS__, __SIZE__) (((__ADDRESS__) & (1<<(__SIZE__+1U))- 1U) == 0U) +#define IS_MPU_ADDRESS_MULTIPLE_SIZE(__ADDRESS__, __SIZE__) (((__ADDRESS__) & ((1<<(__SIZE__+1U))- 1U)) == 0U) /** * @} diff --git a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_def.h b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_def.h index a8c52ffb0..1adf214e0 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_def.h +++ b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_def.h @@ -130,6 +130,10 @@ typedef enum /* Macro to get buffer 32-bytes aligned (aligned to cache line width) */ #define ALIGN_32BYTES(buf) buf __attribute__((aligned(32))) +/* Macro to get buffer 8-bytes aligned (aligned to double-word width) */ +/* This alignment is required for double-word DMA transfers */ +#define ALIGN_8BYTES(buf) buf __attribute__((aligned(8))) + /* Legacy macros to get variable 4-bytes aligned */ #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN diff --git a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_flash_ex.h b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_flash_ex.h index 40e40627e..c74a49210 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_flash_ex.h +++ b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_flash_ex.h @@ -204,8 +204,8 @@ void HAL_FLASHEx_EnableEccDetectionInterrupt(void); void HAL_FLASHEx_DisableEccDetectionInterrupt(void); void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData); void HAL_FLASHEx_ECCD_IRQHandler(void); -__weak void HAL_FLASHEx_EccDetectionCallback(void); -__weak void HAL_FLASHEx_EccCorrectionCallback(void); +void HAL_FLASHEx_EccDetectionCallback(void); +void HAL_FLASHEx_EccCorrectionCallback(void); /** * @} */ diff --git a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_mdios.h b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_mdios.h index 16fd6fc45..5120e1905 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_mdios.h +++ b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_mdios.h @@ -83,7 +83,7 @@ typedef struct typedef struct __MDIOS_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ { MDIOS_TypeDef *Instance; /*!< Register base address */ diff --git a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rcc.h b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rcc.h index 591c5e859..65858d372 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rcc.h +++ b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rcc.h @@ -4103,7 +4103,6 @@ typedef struct * 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 * 150 to 420 MHz if PLL2VCOSEL = 1. * - * (*) : For stm32h7a3xx and stm32h7b3xx family lines. * * @retval None */ @@ -4129,7 +4128,6 @@ typedef struct * @arg RCC_PLL_VCO_HIGH: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) * @arg RCC_PLL_VCO_LOW: Range frequency is between 150 and 420 MHz * - * (*) : For stm32h7a3xx and stm32h7b3xx family lines. * * @retval None */ @@ -4242,7 +4240,6 @@ typedef struct * 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 * 150 to 420 MHz if PLL3VCOSEL = 1. * - * (*) : For stm32h7a3xx and stm32h7b3xx family lines. * * @retval None */ @@ -4266,7 +4263,6 @@ typedef struct * @arg RCC_PLL_VCO_HIGH: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) * @arg RCC_PLL_VCO_HIGH: Range frequency is between 150 and 420 MHz * - * (*) : For stm32h7a3xx and stm32h7b3xx family lines. * * @retval None */ diff --git a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rcc_ex.h b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rcc_ex.h index 23bed741d..2523edda9 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rcc_ex.h +++ b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rcc_ex.h @@ -888,7 +888,7 @@ typedef struct * @arg RCC_FMCCLKSOURCE_HCLK_DIV4 Recovery Clock selected as FMC clock */ #define __HAL_RCC_GET_FMC_SOURCE() ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_FMCSWP) == RCC_FMCCLKSOURCE_HCLK_DIV4) ? \ - RCC_FMCCLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FMCSEL)))) + RCC_FMCCLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FMCSEL)))) /** @brief Macro to configure the I2C1/I3C1 clock source. * @param __I2C1_I3C1_CLKSOURCE__ specifies the I2C1/I3C1clock source. @@ -1070,7 +1070,7 @@ typedef struct * @arg RCC_XSPI1CLKSOURCE_HCLK_DIV4 Recovery Clock selected as XSPI1 clock */ #define __HAL_RCC_GET_XSPI1_SOURCE() ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPI1SWP) == RCC_XSPI1CLKSOURCE_HCLK_DIV4) ? \ - RCC_XSPI1CLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_XSPI1SEL)))) + RCC_XSPI1CLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_XSPI1SEL)))) /** @brief Macro to configure the XSPI2 clock source. * @@ -1090,7 +1090,7 @@ typedef struct * @arg RCC_XSPI2CLKSOURCE_HCLK_DIV4 Recovery Clock selected as XSPI2 clock */ #define __HAL_RCC_GET_XSPI2_SOURCE() ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPI2SWP) == RCC_XSPI2CLKSOURCE_HCLK_DIV4) ? \ - RCC_XSPI2CLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_XSPI2SEL)))) + RCC_XSPI2CLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_XSPI2SEL)))) /** * @brief Macro to configure the PSSI clock source. diff --git a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rng_ex.h b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rng_ex.h index a112097d3..58aa18dd1 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rng_ex.h +++ b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,11 +55,11 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs - value of @ref RNG_Ex_Auto_Reset */ + value of @ref RNGEx_Auto_Reset */ uint32_t HealthTest; /*!< RNG health test control must be a value between 0x0FFCABFF and 0x00005200 */ } RNG_ConfigTypeDef; @@ -69,11 +69,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -112,7 +112,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -121,7 +121,7 @@ typedef struct /** * @} */ -/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration +/** @defgroup RNGEx_Auto_Reset Auto Reset configuration * @{ */ #define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/ @@ -136,7 +136,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -145,7 +145,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -154,7 +154,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -163,7 +163,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -202,7 +202,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -211,11 +211,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -226,7 +226,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); @@ -260,3 +260,4 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); #endif /* STM32H7RSxx_HAL_RNG_EX_H */ + diff --git a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_sdio.h b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_sdio.h index 82e683ab3..8d458b969 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_sdio.h +++ b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_sdio.h @@ -434,19 +434,21 @@ HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDI /** @defgroup SDIO_Exported_Functions_Group3 Process functions * @{ */ -HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData); -HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data); +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument, + uint8_t *pData); +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument, + uint8_t Data); -HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); -HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); -HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte); -HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte); /** * @} @@ -598,3 +600,4 @@ HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio); #endif /* STM32H7RSxx_HAL_SDIO_H */ + diff --git a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_usart_ex.h b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_usart_ex.h index 1878dac81..60af66b1c 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_usart_ex.h +++ b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_hal_usart_ex.h @@ -279,3 +279,4 @@ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, ui #endif #endif /* STM32H7RSxx_HAL_USART_EX_H */ + diff --git a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_dlyb.h b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_dlyb.h index 12a78c3f7..4a4c1135b 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_dlyb.h +++ b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_dlyb.h @@ -31,8 +31,8 @@ extern "C" { * @{ */ -#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED) -#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_OCTOSPI1) || defined (DLYB_OCTOSPI2) +#if defined(HAL_SD_MODULE_ENABLED) +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) /* Exported types ------------------------------------------------------------*/ /** @defgroup DLYB_LL DLYB @@ -129,8 +129,8 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c * @} */ -#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 || DLYB_OCTOSPI1 || DLYB_OCTOSPI2 */ -#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */ +#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 */ +#endif /* HAL_SD_MODULE_ENABLED */ /** * @} diff --git a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_rcc.h b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_rcc.h index ea1a2f2a0..f80ff2acc 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_rcc.h +++ b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_rcc.h @@ -75,7 +75,7 @@ extern "C" { */ #if !defined(UNUSED) #define UNUSED(x) ((void)(x)) -#endif +#endif /* UNUSED */ #define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL) @@ -5445,7 +5445,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) } /** - * @brief Check if RCC flag Low Power D1 reset is set or not. + * @brief Check if RCC flag Low Power reset is set or not. * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST * @retval State of bit (1 or 0). */ diff --git a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_rng.h b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_rng.h index ad4470a0f..4dc1918da 100644 --- a/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_rng.h +++ b/stm32cube/stm32h7rsxx/drivers/include/stm32h7rsxx_ll_rng.h @@ -230,7 +230,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) { - CLEAR_BIT(RNGx->CR, RNG_CR_CED); + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -241,7 +242,8 @@ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) { - SET_BIT(RNGx->CR, RNG_CR_CED); + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -331,7 +333,7 @@ __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) { MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST); - CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);; + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -442,7 +444,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) { - MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, (Divider << RNG_CR_CLKDIV_Pos) | RNG_CR_CONDRST); + MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST); CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } @@ -693,7 +695,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); @@ -721,3 +723,4 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); #endif #endif /* __STM32H7RSxx_LL_RNG_H */ + From 41b00fd04b6664e2095a3aad6382dc978d0ea5f8 Mon Sep 17 00:00:00 2001 From: Fabrice DJIATSA Date: Thu, 17 Apr 2025 09:29:34 +0200 Subject: [PATCH 3/3] stm32cube: stm32h7rsxx: drivers: src: update hal-ll src driver synchronize hal-ll src files with the correct h7rs cube repository history. Signed-off-by: Fabrice DJIATSA --- .../drivers/src/stm32h7rsxx_hal_cryp.c | 6 +- .../drivers/src/stm32h7rsxx_hal_eth.c | 2 +- .../drivers/src/stm32h7rsxx_hal_mmc.c | 4 +- .../drivers/src/stm32h7rsxx_hal_rcc.c | 61 ++++++++-------- .../drivers/src/stm32h7rsxx_hal_rng.c | 5 +- .../drivers/src/stm32h7rsxx_hal_rng_ex.c | 11 +-- .../drivers/src/stm32h7rsxx_hal_sd.c | 2 +- .../drivers/src/stm32h7rsxx_hal_sdio.c | 70 +++++++++++-------- ...2h7rsxx_hal_timebase_rtc_wakeup_template.c | 2 +- .../stm32h7rsxx_hal_timebase_tim_template.c | 7 +- .../drivers/src/stm32h7rsxx_ll_crs.c | 2 - .../drivers/src/stm32h7rsxx_ll_dlyb.c | 8 +-- .../drivers/src/stm32h7rsxx_ll_rcc.c | 27 ++++--- .../drivers/src/stm32h7rsxx_ll_rng.c | 3 +- .../drivers/src/stm32h7rsxx_ll_spi.c | 4 +- 15 files changed, 117 insertions(+), 97 deletions(-) diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_cryp.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_cryp.c index 01efac245..59ea38258 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_cryp.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_cryp.c @@ -7112,7 +7112,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u { /* Enter last bytes, padded with zeros */ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + tmp &= mask[(SAES_CONV_DATATYPE(hcryp->Init.DataType) * 2U) + (headersize_in_bytes % 4U)]; ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp; loopcounter++; /* Pad the data with zeros to have a complete block */ @@ -7378,7 +7378,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry { /* Enter last bytes, padded with zeros */ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + tmp &= mask[(SAES_CONV_DATATYPE(hcryp->Init.DataType) * 2U) + (headersize_in_bytes % 4U)]; ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp; loopcounter++; /* Pad the data with zeros to have a complete block */ @@ -7667,7 +7667,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) { /* Enter last bytes, padded with zeros */ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + tmp &= mask[(SAES_CONV_DATATYPE(hcryp->Init.DataType) * 2U) + (headersize_in_bytes % 4U)]; ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp; loopcounter++; hcryp->CrypHeaderCount++; diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_eth.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_eth.c index c6fd1e318..64aa1a855 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_eth.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_eth.c @@ -1990,7 +1990,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) if ((mac_flag & ETH_MAC_LPI_IT) != 0U) { /* Get MAC LPI interrupt source and clear the status register pending bit */ - heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU); + heth->MACLPIEvent = READ_BIT(heth->Instance->MACLCSR, 0x0000000FU); #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /* Call registered EEE callback*/ diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_mmc.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_mmc.c index e1e93f0f6..0c69ea75a 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_mmc.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_mmc.c @@ -486,7 +486,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) { uint32_t errorstate; - MMC_InitTypeDef Init; + MMC_InitTypeDef Init = {0U}; uint32_t sdmmc_clk; /* Default SDMMC peripheral configuration for MMC card initialization */ @@ -3986,7 +3986,7 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) uint32_t response = 0U; uint32_t count; uint32_t sdmmc_clk; - SDMMC_InitTypeDef Init; + SDMMC_InitTypeDef Init = {0U}; if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE)) { diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_rcc.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_rcc.c index d5b614b86..6af6d0edd 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_rcc.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_rcc.c @@ -41,8 +41,7 @@ (+) Configure the AHB and APB buses pre-scalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock kernel source(s) for peripherals which clocks are not - derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R - and RCC_D3CCIPR registers + derived from the System clock. ##### RCC Limitations ##### ============================================================================== @@ -193,15 +192,10 @@ static HAL_StatusTypeDef RCC_PLL_Config(uint32_t PLLnumber, const RCC_PLLInitTyp HSE and PLL. The AHB clock (HCLK) is derived from System core clock through configurable pre-scaler and used to clock the CPU, memory and peripherals mapped - on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers + on AHB and APB bus through configurable pre-scalers and used to clock the peripherals mapped on these buses. You can use "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency. - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those - with dual clock domain where kernel source clock could be selected through - RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers. - - (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines. @endverbatim * @{ */ @@ -248,7 +242,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) /* Reset CFGR register (HSI is selected as system clock source) */ CLEAR_REG(RCC->CFGR); - /* Update the SystemCoreClock and SystemD2Clock global variables */ + /* Update the SystemCoreClock global variables */ SystemCoreClock = HSI_VALUE; /* Adapt Systick interrupt period */ @@ -874,8 +868,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * occur when the clock source will be ready. * You can use HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. - * @note Depending on the device voltage range, the software has to set correctly - * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ @@ -1255,9 +1247,15 @@ void HAL_RCC_DisableCSS(void) */ uint32_t HAL_RCC_GetSysClockFreq(void) { - uint32_t pllp, pllsource, pllm, pllfracen, hsivalue; - float_t fracn1, pllvco; - uint32_t sysclockfreq, prescaler; + uint32_t pllp; + uint32_t pllsource; + uint32_t pllm; + uint32_t pllfracen; + uint32_t hsivalue; + float_t fracn1; + float_t pllvco; + uint32_t sysclockfreq; + uint32_t prescaler; /* Get SYSCLK source -------------------------------------------------------*/ @@ -1355,7 +1353,8 @@ uint32_t HAL_RCC_GetSysClockFreq(void) */ uint32_t HAL_RCC_GetHCLKFreq(void) { - uint32_t clock, prescaler; + uint32_t clock; + uint32_t prescaler; const uint8_t AHBPrescTable[8] = {1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; /* SysClk */ @@ -1377,7 +1376,8 @@ uint32_t HAL_RCC_GetHCLKFreq(void) */ uint32_t HAL_RCC_GetPCLK1Freq(void) { - uint32_t clock, prescaler; + uint32_t clock; + uint32_t prescaler; /* Get HCLK source and compute PCLK1 frequency ---------------------------*/ clock = HAL_RCC_GetHCLKFreq(); /* APB1 prescaler */ @@ -1397,7 +1397,8 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) */ uint32_t HAL_RCC_GetPCLK2Freq(void) { - uint32_t clock, prescaler; + uint32_t clock; + uint32_t prescaler; /* Get HCLK source and compute PCLK2 frequency ---------------------------*/ clock = HAL_RCC_GetHCLKFreq(); /* APB2 prescaler */ @@ -1417,7 +1418,8 @@ uint32_t HAL_RCC_GetPCLK2Freq(void) */ uint32_t HAL_RCC_GetPCLK4Freq(void) { - uint32_t clock, prescaler; + uint32_t clock; + uint32_t prescaler; /* Get HCLK source and compute PCLK4 frequency ---------------------------*/ clock = HAL_RCC_GetHCLKFreq(); /* APB4 prescaler */ @@ -1437,7 +1439,8 @@ uint32_t HAL_RCC_GetPCLK4Freq(void) */ uint32_t HAL_RCC_GetPCLK5Freq(void) { - uint32_t clock, prescaler; + uint32_t clock; + uint32_t prescaler; /* Get HCLK source and compute PCLK5 frequency ---------------------------*/ clock = HAL_RCC_GetHCLKFreq(); /* APB5 prescaler */ @@ -2100,7 +2103,7 @@ static uint32_t RCC_PLL1_GetVCOOutputFreq(void) uint32_t pllfracn; float_t frequency; - /* Get PLL1 CFGR and DIVR register values */ + /* Get PLL1 CKSELR and DIVR register values */ tmpreg1 = RCC->PLLCKSELR; tmpreg2 = RCC->PLL1DIVR1; @@ -2115,7 +2118,7 @@ static uint32_t RCC_PLL1_GetVCOOutputFreq(void) } /* Check if fractional part is enable */ - if ((tmpreg1 & RCC_PLLCFGR_PLL1FRACEN) != 0U) + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) != 0U) { pllfracn = (RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN) >> RCC_PLL1FRACR_FRACN_Pos; } @@ -2154,10 +2157,10 @@ static uint32_t RCC_PLL1_GetVCOOutputFreq(void) pllsrc = 0U; break; } - + /* Compute VCO output frequency */ frequency = ((float_t)pllsrc / (float_t)pllm) * ((float_t)plln + ((float_t)pllfracn / (float_t)0x2000U)); - + return (uint32_t)frequency; } @@ -2175,7 +2178,7 @@ static uint32_t RCC_PLL2_GetVCOOutputFreq(void) uint32_t pllfracn; float_t frequency; - /* Get PLL2 CFGR and DIVR register values */ + /* Get PLL2 CKSELR and DIVR register values */ tmpreg1 = RCC->PLLCKSELR; tmpreg2 = RCC->PLL2DIVR1; @@ -2190,7 +2193,7 @@ static uint32_t RCC_PLL2_GetVCOOutputFreq(void) } /* Check if fractional part is enable */ - if ((tmpreg1 & RCC_PLLCFGR_PLL2FRACEN) != 0U) + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) != 0U) { pllfracn = (RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN) >> RCC_PLL2FRACR_FRACN_Pos; } @@ -2232,7 +2235,7 @@ static uint32_t RCC_PLL2_GetVCOOutputFreq(void) /* Compute VCO output frequency */ frequency = ((float_t)pllsrc / (float_t)pllm) * ((float_t)plln + ((float_t)pllfracn / (float_t)0x2000U)); - + return (uint32_t)frequency; } @@ -2250,7 +2253,7 @@ static uint32_t RCC_PLL3_GetVCOOutputFreq(void) uint32_t pllfracn; float_t frequency; - /* Get PLL3 CFGR and DIVR register values */ + /* Get PLL3 CKSELR and DIVR register values */ tmpreg1 = RCC->PLLCKSELR; tmpreg2 = RCC->PLL3DIVR1; @@ -2265,7 +2268,7 @@ static uint32_t RCC_PLL3_GetVCOOutputFreq(void) } /* Check if fractional part is enable */ - if ((tmpreg1 & RCC_PLLCFGR_PLL3FRACEN) != 0U) + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) != 0U) { pllfracn = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN) >> RCC_PLL3FRACR_FRACN_Pos; } @@ -2307,7 +2310,7 @@ static uint32_t RCC_PLL3_GetVCOOutputFreq(void) /* Compute VCO output frequency */ frequency = ((float_t)pllsrc / (float_t)pllm) * ((float_t)plln + ((float_t)pllfracn / (float_t)0x2000U)); - + return (uint32_t)frequency; } diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_rng.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_rng.c index 2a2c03b70..b114b250f 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_rng.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_rng.c @@ -233,7 +233,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Get tick */ tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ - while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { @@ -676,8 +676,6 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Update the error code and status */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; status = HAL_ERROR; - /* Clear bit DRDY */ - CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY); } else /* No seed error */ { @@ -1026,3 +1024,4 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) /** * @} */ + diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_rng_ex.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_rng_ex.c index 311e923cc..a78c6c118 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_rng_ex.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_rng_ex.c @@ -30,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNG_Ex +/** @addtogroup RNGEx * @brief RNG Extended HAL module driver. * @{ */ @@ -41,7 +41,7 @@ /* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Private_Constants +/** @addtogroup RNGEx_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -53,11 +53,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions * @{ */ -/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -269,7 +269,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim @@ -341,3 +341,4 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /** * @} */ + diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_sd.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_sd.c index 467708337..136e0a9dc 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_sd.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_sd.c @@ -465,7 +465,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { uint32_t errorstate; - SD_InitTypeDef Init; + SD_InitTypeDef Init = {0U}; uint32_t sdmmc_clk; /* Default SDMMC peripheral configuration for SD card initialization */ diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_sdio.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_sdio.c index 20c8d701f..fd8fc4b99 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_sdio.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_sdio.c @@ -256,18 +256,18 @@ #define IS_SDIO_FUNCTION(FN) (((FN) >= HAL_SDIO_FUNCTION_1) && ((FN) <= HAL_SDIO_FUNCTION_7)) -#define IS_SDIO_SUPPORTED_BLOCK_SIZE(BLOCKSIZE) (((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_4BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_8BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_16BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_32BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_64BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_128BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_256BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE)) +#define IS_SDIO_SUPPORTED_BLOCK_SIZE(SDIO_BLOCKSIZE) (((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_4BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_8BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_16BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_32BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_64BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_128BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_256BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE)) /* Private functions -------------------------------------------------------------------------------------------------*/ /** @defgroup SDIO_Private_Functions SDIO Private Functions @@ -277,10 +277,10 @@ static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio); static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, uint8_t *pData); static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, - uint8_t *pData); + const uint8_t *pData); static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, uint8_t *pData, uint16_t Size_byte); -static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size); +static uint8_t SDIO_Convert_Block_Size(const SDIO_HandleTypeDef *hsdio, uint32_t block_size); static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio); /** * @} @@ -312,7 +312,7 @@ static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio); */ HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) { - SDIO_InitTypeDef Init; + SDIO_InitTypeDef Init = {0U}; uint32_t sdmmc_clk; uint8_t data; @@ -376,8 +376,15 @@ HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) (void)SDMMC_PowerState_ON(hsdio->Instance); /* wait 74 Cycles: required power up waiting time before starting the SDIO initialization sequence */ - sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); - HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + if (Init.ClockDiv != 0U) + { + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + } + + if (sdmmc_clk != 0U) + { + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + } if (hsdio->SDIO_IdentifyCard == NULL) { @@ -805,7 +812,8 @@ HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDI * @param pData: pointer to the buffer that will contain the received data. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData) +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument, + uint8_t *pData) { uint32_t cmd; uint32_t errorstate; @@ -870,7 +878,8 @@ HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Direct * @param Data: pointer to the buffer that will contain the received data. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data) +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument, + uint8_t Data) { uint32_t cmd; uint32_t errorstate; @@ -934,7 +943,7 @@ HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Direc * @param Timeout_Ms: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms) { uint32_t cmd; @@ -1051,7 +1060,7 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Exte } else if (dataremaining < 32U) { - while ((dataremaining > 0U) && !(__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOE))) + while (!(__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOE)) && (dataremaining > 0U)) { data = SDMMC_ReadFIFO(hsdio->Instance); for (byteCount = 0U; byteCount < 4U; byteCount++) @@ -1143,7 +1152,7 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Exte * @param Timeout_Ms: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms) { uint32_t cmd; @@ -1246,9 +1255,9 @@ HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Ext } dataremaining -= 32U; } - else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE))) + else if ((__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE)) && (dataremaining < 32U)) { - uint8_t *u8buff = (uint8_t *)u32tempbuff; + const uint8_t *u8buff = (uint8_t *)u32tempbuff; while (dataremaining > 0U) { data = 0U; @@ -1335,7 +1344,7 @@ HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Ext * @param Size_byte: Block size to write. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte) { SDMMC_DataInitTypeDef config; @@ -1467,7 +1476,7 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ * @param Size_byte: Block size to write. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte) { uint32_t cmd; @@ -1665,7 +1674,6 @@ void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio) } hsdio->Context = SDIO_CONTEXT_NONE; - hsdio->State = HAL_SDIO_STATE_READY; } if (hsdio->remaining_data != 0U) @@ -2606,7 +2614,7 @@ static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t add * @retval HAL status */ static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, - uint32_t function_nbr, uint8_t *pData) + uint32_t function_nbr, const uint8_t *pData) { uint32_t errorstate; uint32_t cmd; @@ -2728,9 +2736,9 @@ static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ } dataremaining -= 32U; } - else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE))) + else if ((__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE)) && (dataremaining < 32U)) { - uint8_t *u8buff = (uint8_t *)u32tempbuff; + const uint8_t *u8buff = (uint8_t *)u32tempbuff; while (dataremaining > 0U) { data = 0U; @@ -2801,7 +2809,7 @@ static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ * @param block_size: block size in bytes * @retval block size as DBLOCKSIZE[3:0] bits format */ -static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size) +static uint8_t SDIO_Convert_Block_Size(const SDIO_HandleTypeDef *hsdio, uint32_t block_size) { UNUSED(hsdio); diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_timebase_rtc_wakeup_template.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_timebase_rtc_wakeup_template.c index 3c4ebb99d..3c60f62cd 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_timebase_rtc_wakeup_template.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_timebase_rtc_wakeup_template.c @@ -249,7 +249,7 @@ void HAL_ResumeTick(void) void TimeBase_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) #else void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1U */ { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_timebase_tim_template.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_timebase_tim_template.c index be1d600ad..08a8a6da8 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_timebase_tim_template.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_hal_timebase_tim_template.c @@ -132,6 +132,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) Status = HAL_TIM_Base_Init(&TimHandle); if (Status == HAL_OK) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Start the TIM time Base generation in interrupt mode */ Status = HAL_TIM_Base_Start_IT(&TimHandle); if (Status == HAL_OK) @@ -152,9 +156,6 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) } } } -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) - HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Return function status */ return Status; diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_crs.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_crs.c index 52364739a..c6702f248 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_crs.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_crs.c @@ -60,8 +60,6 @@ ErrorStatus LL_CRS_DeInit(void) return SUCCESS; } - - /** * @} */ diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_dlyb.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_dlyb.c index b08713f7a..9a2b969a1 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_dlyb.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_dlyb.c @@ -60,8 +60,8 @@ * @{ */ -#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED) -#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_OCTOSPI1) || defined (DLYB_OCTOSPI2) +#if defined(HAL_SD_MODULE_ENABLED) +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) /** @cond 0 @@ -231,8 +231,8 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c /** * @} */ -#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 || DLYB_OCTOSPI1 || DLYB_OCTOSPI2 */ -#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */ +#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 */ +#endif /* HAL_SD_MODULE_ENABLED */ /** * @} diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_rcc.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_rcc.c index 4c5a9ef02..475fa1f47 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_rcc.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_rcc.c @@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_LL_DRIVER */ /** @addtogroup STM32H7RSxx_LL_Driver * @{ @@ -312,8 +312,11 @@ void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) */ void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) { - uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource; - uint32_t m, n, fracn = 0U; + uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO; + uint32_t pllsource; + uint32_t m; + uint32_t n; + uint32_t fracn = 0U; /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) SYSCLK = PLL_VCO / PLLP @@ -396,8 +399,11 @@ void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) */ void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) { - uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource; - uint32_t m, n, fracn = 0U; + uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO; + uint32_t pllsource; + uint32_t m; + uint32_t n; + uint32_t fracn = 0U; /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) SYSCLK = PLL_VCO / PLLP @@ -485,8 +491,11 @@ void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) */ void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) { - uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource; - uint32_t m, n, fracn = 0U; + uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO; + uint32_t pllsource; + uint32_t m; + uint32_t n; + uint32_t fracn = 0U; /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) SYSCLK = PLL_VCO / PLLP @@ -1705,7 +1714,7 @@ uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource) case LL_RCC_FMC_CLKSOURCE_HCLK_DIV4: fmc_frequency = (RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())) / 4U); - break; + break; default: /* Nothing to do */ @@ -1783,7 +1792,7 @@ uint32_t LL_RCC_GetXSPIClockFreq(uint32_t XSPIxSource) case LL_RCC_XSPI1_CLKSOURCE_HCLK_DIV4: case LL_RCC_XSPI2_CLKSOURCE_HCLK_DIV4: xspi_frequency = (RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())) / 4U); - break; + break; default: /* Nothing to do */ diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_rng.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_rng.c index 5bfb00a5e..2e26527b2 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_rng.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_rng.c @@ -110,7 +110,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content * - ERROR: not applicable */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); @@ -155,3 +155,4 @@ void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ + diff --git a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_spi.c b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_spi.c index f2f1055a5..8080ef348 100644 --- a/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_spi.c +++ b/stm32cube/stm32h7rsxx/drivers/src/stm32h7rsxx_ll_spi.c @@ -646,10 +646,10 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStr else if ((SPIx == SPI2) || (SPIx == SPI3)) { sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI23_CLKSOURCE); - } + } else /* SPI6 */ { - sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE); + sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE); } /* Compute the Real divider depending on the MCLK output state with a fixed point */