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求解的过程手动推导了一下，https://learnblockchain.cn/article/6189 |
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paper 来源：https://eprint.iacr.org/2019/317.pdf
gate的输入u 和 v既然是在extended field上，但在实际电路里并没有相应的引脚，verifier 如何计算ADD 和 MUL 呢？
比如这个电路， 如果第0层sample 的是第三个也就是0，假定是ADD gate的话，它的第1层输入应该有很多个组合，但问题是并没有第1层的gate wire 指向这个0。
问题的根源在于如何拿到ADD/MUL 的MLE(multi linear extension) 表达式？
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