From e16390dc8f53695fad0af532b45ec4c6a2319df4 Mon Sep 17 00:00:00 2001 From: Takahiro Date: Thu, 9 Apr 2020 21:46:14 -0700 Subject: [PATCH] Non misleading bit width expression in chapter C (#506) --- src/c.tex | 68 +++++++++++++++++++++++++++---------------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/src/c.tex b/src/c.tex index af8aca70a..295a89364 100644 --- a/src/c.tex +++ b/src/c.tex @@ -398,7 +398,7 @@ \subsection*{Stack-Pointer-Based Loads and Stores} C.LWSP loads a 32-bit value from memory into register {\em rd}. It computes an effective address by adding the {\em zero}-extended offset, scaled by 4, to -the stack pointer, {\tt x2}. It expands to {\tt lw rd, offset[7:2](x2)}. +the stack pointer, {\tt x2}. It expands to {\tt lw rd, offset(x2)}. C.LWSP is only valid when $\textit{rd}{\neq}\texttt{x0}$; the code points with $\textit{rd}{=}\texttt{x0}$ are reserved. @@ -406,14 +406,14 @@ \subsection*{Stack-Pointer-Based Loads and Stores} C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into register {\em rd}. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, {\tt x2}. -It expands to {\tt ld rd, offset[8:3](x2)}. +It expands to {\tt ld rd, offset(x2)}. C.LDSP is only valid when $\textit{rd}{\neq}\texttt{x0}$; the code points with $\textit{rd}{=}\texttt{x0}$ are reserved. C.LQSP is an RV128C-only instruction that loads a 128-bit value from memory into register {\em rd}. It computes its effective address by adding the zero-extended offset, scaled by 16, to the stack pointer, {\tt x2}. -It expands to {\tt lq rd, offset[9:4](x2)}. +It expands to {\tt lq rd, offset(x2)}. C.LQSP is only valid when $\textit{rd}{\neq}\texttt{x0}$; the code points with $\textit{rd}{=}\texttt{x0}$ are reserved. @@ -421,13 +421,13 @@ \subsection*{Stack-Pointer-Based Loads and Stores} floating-point value from memory into floating-point register {\em rd}. It computes its effective address by adding the {\em zero}-extended offset, scaled by 4, to the stack pointer, {\tt x2}. It expands to {\tt flw rd, -offset[7:2](x2)}. +offset(x2)}. C.FLDSP is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register {\em rd}. It computes its effective address by adding the {\em zero}-extended offset, scaled by 8, to the stack pointer, {\tt x2}. It expands to {\tt fld rd, -offset[8:3](x2)}. +offset(x2)}. \begin{center} \begin{tabular}{S@{}M@{}T@{}Y} @@ -455,29 +455,29 @@ \subsection*{Stack-Pointer-Based Loads and Stores} C.SWSP stores a 32-bit value in register {\em rs2} to memory. It computes an effective address by adding the {\em zero}-extended offset, scaled by 4, to the stack pointer, {\tt x2}. -It expands to {\tt sw rs2, offset[7:2](x2)}. +It expands to {\tt sw rs2, offset(x2)}. C.SDSP is an RV64C/RV128C-only instruction that stores a 64-bit value in register {\em rs2} to memory. It computes an effective address by adding the {\em zero}-extended offset, scaled by 8, to the stack pointer, {\tt x2}. -It expands to {\tt sd rs2, offset[8:3](x2)}. +It expands to {\tt sd rs2, offset(x2)}. C.SQSP is an RV128C-only instruction that stores a 128-bit value in register {\em rs2} to memory. It computes an effective address by adding the {\em zero}-extended offset, scaled by 16, to the stack pointer, {\tt x2}. -It expands to {\tt sq rs2, offset[9:4](x2)}. +It expands to {\tt sq rs2, offset(x2)}. C.FSWSP is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register {\em rs2} to memory. It computes an effective address by adding the {\em zero}-extended offset, scaled by 4, to the stack pointer, {\tt x2}. It expands to {\tt fsw rs2, -offset[7:2](x2)}. +offset(x2)}. C.FSDSP is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register {\em rs2} to memory. It computes an effective address by adding the {\em zero}-extended offset, scaled by 8, to the stack pointer, {\tt x2}. It expands to {\tt fsd rs2, -offset[8:3](x2)}. +offset(x2)}. \begin{commentary} Register save/restore code at function entry/exit represents a @@ -551,31 +551,31 @@ \subsection*{Register-Based Loads and Stores} C.LW loads a 32-bit value from memory into register {\em \rdprime}. It computes an effective address by adding the {\em zero}-extended offset, scaled by 4, to the base address in register {\em \rsoneprime}. -It expands to {\tt lw \rdprime, offset[6:2](\rsoneprime)}. +It expands to {\tt lw \rdprime, offset(\rsoneprime)}. C.LD is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into register {\em \rdprime}. It computes an effective address by adding the {\em zero}-extended offset, scaled by 8, to the base address in register {\em \rsoneprime}. -It expands to {\tt ld \rdprime, offset[7:3](\rsoneprime)}. +It expands to {\tt ld \rdprime, offset(\rsoneprime)}. C.LQ is an RV128C-only instruction that loads a 128-bit value from memory into register {\em \rdprime}. It computes an effective address by adding the {\em zero}-extended offset, scaled by 16, to the base address in register {\em \rsoneprime}. -It expands to {\tt lq \rdprime, offset[8:4](\rsoneprime)}. +It expands to {\tt lq \rdprime, offset(\rsoneprime)}. C.FLW is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register {\em \rdprime}. It computes an effective address by adding the {\em zero}-extended offset, scaled by 4, to the base address in register {\em \rsoneprime}. It expands to {\tt flw -\rdprime, offset[6:2](\rsoneprime)}. +\rdprime, offset(\rsoneprime)}. C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register {\em \rdprime}. It computes an effective address by adding the {\em zero}-extended offset, scaled by 8, to the base address in register {\em \rsoneprime}. It expands to {\tt fld -\rdprime, offset[7:3](\rsoneprime)}. +\rdprime, offset(\rsoneprime)}. \begin{center} \begin{tabular}{S@{}S@{}S@{}Y@{}S@{}Y} @@ -607,31 +607,31 @@ \subsection*{Register-Based Loads and Stores} C.SW stores a 32-bit value in register {\em \rstwoprime} to memory. It computes an effective address by adding the {\em zero}-extended offset, scaled by 4, to the base address in register {\em \rsoneprime}. -It expands to {\tt sw \rstwoprime, offset[6:2](\rsoneprime)}. +It expands to {\tt sw \rstwoprime, offset(\rsoneprime)}. C.SD is an RV64C/RV128C-only instruction that stores a 64-bit value in register {\em \rstwoprime} to memory. It computes an effective address by adding the {\em zero}-extended offset, scaled by 8, to the base address in register {\em \rsoneprime}. -It expands to {\tt sd \rstwoprime, offset[7:3](\rsoneprime)}. +It expands to {\tt sd \rstwoprime, offset(\rsoneprime)}. C.SQ is an RV128C-only instruction that stores a 128-bit value in register {\em \rstwoprime} to memory. It computes an effective address by adding the {\em zero}-extended offset, scaled by 16, to the base address in register {\em \rsoneprime}. -It expands to {\tt sq \rstwoprime, offset[8:4](\rsoneprime)}. +It expands to {\tt sq \rstwoprime, offset(\rsoneprime)}. C.FSW is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register {\em \rstwoprime} to memory. It computes an effective address by adding the {\em zero}-extended offset, scaled by 4, to the base address in register {\em \rsoneprime}. It expands to {\tt fsw -\rstwoprime, offset[6:2](\rsoneprime)}. +\rstwoprime, offset(\rsoneprime)}. C.FSD is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register {\em \rstwoprime} to memory. It computes an effective address by adding the {\em zero}-extended offset, scaled by 8, to the base address in register {\em \rsoneprime}. It expands to {\tt fsd -\rstwoprime, offset[7:3](\rsoneprime)}. +\rstwoprime, offset(\rsoneprime)}. \section{Control Transfer Instructions} @@ -659,12 +659,12 @@ \section{Control Transfer Instructions} C.J performs an unconditional control transfer. The offset is sign-extended and added to the {\tt pc} to form the jump target address. C.J can therefore target -a $\pm$\wunits{2}{KiB} range. C.J expands to {\tt jal x0, offset[11:1]}. +a $\pm$\wunits{2}{KiB} range. C.J expands to {\tt jal x0, offset}. C.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump ({\tt pc}+2) to the link register, {\tt x1}. C.JAL expands to {\tt jal x1, -offset[11:1]}. +offset}. \begin{center} \begin{tabular}{E@{}T@{}T@{}Y} @@ -731,10 +731,10 @@ \section{Control Transfer Instructions} and added to the {\tt pc} to form the branch target address. It can therefore target a $\pm$\wunits{256}{B} range. C.BEQZ takes the branch if the value in register {\em \rsoneprime} is zero. It expands to {\tt beq \rsoneprime, x0, -offset[8:1]}. +offset}. C.BNEZ is defined analogously, but it takes the branch if {\em \rsoneprime} contains -a nonzero value. It expands to {\tt bne \rsoneprime, x0, offset[8:1]}. +a nonzero value. It expands to {\tt bne \rsoneprime, x0, offset}. \section{Integer Computational Instructions} @@ -768,14 +768,14 @@ \subsection*{Integer Constant-Generation Instructions} \end{center} C.LI loads the sign-extended 6-bit immediate, {\em imm}, into register {\em rd}. -C.LI expands into {\tt addi rd, x0, imm[5:0]}. +C.LI expands into {\tt addi rd, x0, imm}. C.LI is only valid when {\em rd}$\neq${\tt x0}; the code points with {\em rd}={\tt x0} encode HINTs. C.LUI loads the non-zero 6-bit immediate field into bits 17--12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. -C.LUI expands into {\tt lui rd, nzimm[17:12]}. +C.LUI expands into {\tt lui rd, nzimm}. C.LUI is only valid when $\textit{rd}{\neq}{\left\{\texttt{x0},\texttt{x2}\right\}}$, and when the immediate is not equal to zero. @@ -814,14 +814,14 @@ \subsection*{Integer Register-Immediate Operations} C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register {\em rd} then writes the result to {\em rd}. C.ADDI expands -into {\tt addi rd, rd, nzimm[5:0]}. +into {\tt addi rd, rd, nzimm}. C.ADDI is only valid when {\em rd}$\neq${\tt x0} and {\em nzimm}$\neq$0. The code points with {\em rd}={\tt x0} encode the C.NOP instruction; the remaining code points with {\em nzimm}=0 encode HINTs. C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to -64 bits. C.ADDIW expands into {\tt addiw rd, rd, imm[5:0]}. The +64 bits. C.ADDIW expands into {\tt addiw rd, rd, imm}. The immediate can be zero for C.ADDIW, where this corresponds to {\tt sext.w rd}. C.ADDIW is only valid when {\em rd}$\neq${\tt x0}; the code points with {\em rd}={\tt x0} are reserved. @@ -831,7 +831,7 @@ \subsection*{Integer Register-Immediate Operations} the value in the stack pointer ({\tt sp}={\tt x2}), where the immediate is scaled to represent multiples of 16 in the range (-512,496). C.ADDI16SP is used to adjust the stack pointer in procedure -prologues and epilogues. It expands into {\tt addi x2, x2, nzimm[9:4]}. +prologues and epilogues. It expands into {\tt addi x2, x2, nzimm}. C.ADDI16SP is only valid when {\em nzimm}$\neq$0; the code point with {\em nzimm}=0 is reserved. @@ -862,7 +862,7 @@ \subsection*{Integer Register-Immediate Operations} non-zero immediate, scaled by 4, to the stack pointer, {\tt x2}, and writes the result to {\tt \rdprime}. This instruction is used to generate pointers to stack-allocated variables, and expands to -{\tt addi \rdprime, x2, nzuimm[9:2]}. +{\tt addi \rdprime, x2, nzuimm}. C.ADDI4SPN is only valid when {\em nzuimm}$\neq$0; the code points with {\em nzuimm}=0 are reserved. @@ -891,7 +891,7 @@ \subsection*{Integer Register-Immediate Operations} of the value in register {\em rd} then writes the result to {\em rd}. The shift amount is encoded in the {\em shamt} field. For RV128C, a shift amount of zero is used to encode a shift of 64. -C.SLLI expands into {\tt slli rd, rd, shamt[5:0]}, except for +C.SLLI expands into {\tt slli rd, rd, shamt}, except for RV128C with {\tt shamt=0}, which expands to {\tt slli rd, rd, 64}. For RV32C, {\em shamt[5]} must be zero; the code points with {\em shamt[5]}=1 @@ -930,7 +930,7 @@ \subsection*{Integer Register-Immediate Operations} For RV128C, a shift amount of zero is used to encode a shift of 64. Furthermore, the shift amount is sign-extended for RV128C, and so the legal shift amounts are 1--31, 64, and 96--127. -C.SRLI expands into {\tt srli \rdprime, \rdprime, shamt[5:0]}, +C.SRLI expands into {\tt srli \rdprime, \rdprime, shamt}, except for RV128C with {\tt shamt=0}, which expands to {\tt srli \rdprime, \rdprime, 64}. @@ -940,7 +940,7 @@ \subsection*{Integer Register-Immediate Operations} C.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic right shift. -C.SRAI expands to {\tt srai \rdprime, \rdprime, shamt[5:0]}. +C.SRAI expands to {\tt srai \rdprime, \rdprime, shamt}. \begin{commentary} Left shifts are usually more frequent than right shifts, as left @@ -981,7 +981,7 @@ \subsection*{Integer Register-Immediate Operations} C.ANDI is a CB-format instruction that computes the bitwise AND of the value in register {\em \rdprime} and the sign-extended 6-bit immediate, then writes the result to {\em \rdprime}. -C.ANDI expands to {\tt andi \rdprime, \rdprime, imm[5:0]}. +C.ANDI expands to {\tt andi \rdprime, \rdprime, imm}. \subsection*{Integer Register-Register Operations} \vspace{-0.4in}