From 470a973251cd719786d990920e1a34858ba9e99c Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 16 Apr 2020 17:55:02 -0700
Subject: [PATCH] Clarify that the EEI defines misaligned FP ld/st behavior

---
 src/f.tex    | 4 ++++
 src/rv32.tex | 1 +
 2 files changed, 5 insertions(+)

diff --git a/src/f.tex b/src/f.tex
index a9022c42d..372a4ebec 100644
--- a/src/f.tex
+++ b/src/f.tex
@@ -370,6 +370,10 @@ \section{Single-Precision Load and Store Instructions}
 FLW and FSW do not modify the bits being transferred; in particular, the
 payloads of non-canonical NaNs are preserved.
 
+As described in Section~\ref{sec:rv32:ldst}, the EEI defines whether
+misaligned floating-point loads and stores are handled invisibly or raise
+a contained or fatal trap.
+
 \section{Single-Precision Floating-Point Computational Instructions}
 \label{sec:single-float-compute}
 
diff --git a/src/rv32.tex b/src/rv32.tex
index 67b2cbc74..fbafdae1b 100644
--- a/src/rv32.tex
+++ b/src/rv32.tex
@@ -994,6 +994,7 @@ \subsubsection*{Conditional Branches}
 \end{commentary}
 
 \section{Load and Store Instructions}
+\label{sec:rv32:ldst}
 
 RV32I is a load-store architecture, where only load and store
 instructions access memory and arithmetic instructions only operate on