From 0e6e1d4f440116d604356f5b4aa04765f9663502 Mon Sep 17 00:00:00 2001 From: Jonathan Behrens Date: Thu, 23 Apr 2020 23:30:46 -0400 Subject: [PATCH] Clarify semantics of sfence.vma with rs1 != 0 (#515) Based on discussion on the mailing list, the instruction fences accesses not just to one leaf PTE but to any leaf PTE that includes the address (subject to address space constraints specified via rs2). --- src/supervisor.tex | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/supervisor.tex b/src/supervisor.tex index e578ddd3e..fca210f1d 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1041,10 +1041,10 @@ \subsection{Supervisor Memory-Management Fence Instruction} Accesses to {\em global} mappings (see Section~\ref{sec:translation}) are not ordered. \item If {\em rs1}$\neq${\tt x0} and {\em rs2}={\tt x0}, the fence orders - only reads and writes made to the leaf page table entry corresponding + only reads and writes made to leaf page table entries corresponding to the virtual address in {\em rs1}, for all address spaces. \item If {\em rs1}$\neq${\tt x0} and {\em rs2}$\neq${\tt x0}, the fence - orders only reads and writes made to the leaf page table entry + orders only reads and writes made to leaf page table entries corresponding to the virtual address in {\em rs1}, for the address space identified by integer register {\em rs2}. Accesses to global mappings are not ordered.