test_cacti_cache.cfg

-size (bytes) 32768
-associativity 4
-read-write port 0
-cache type "cache"
-block size (bytes) 8
-search port 0
-output/input bus width 64
-exclusive write port 3
-exclusive read port 1
-UCA bank count 2
-Power Gating - "false"
-Power Gating Performance Loss 0.01
-single ended read ports 0
-technology (u) 0.040
-page size (bits) 8192
-burst length 8
-internal prefetch width 8
-Data array cell type - "itrs-hp"
-Tag array cell type - "itrs-hp"
-Data array peripheral type - "itrs-hp"
-Tag array peripheral type - "itrs-hp"
-hp Vdd (V) "default"
-lstp Vdd (V) "default"
-lop Vdd (V) "default"
-Long channel devices - "true"
-operating temperature (K) 300
-tag size (b) "default"
-access mode (normal, sequential, fast) - "normal"
-design objective (weight delay, dynamic power, leakage power, cycle time, area) 0:0:0:100:0
-deviate (delay, dynamic power, leakage power, cycle time, area) 20:100000:100000:100000:100000
-NUCAdesign objective (weight delay, dynamic power, leakage power, cycle time, area) 100:100:0:0:100
-NUCAdeviate (delay, dynamic power, leakage power, cycle time, area) 10:10000:10000:10000:10000
-Optimize ED or ED^2 (ED, ED^2, NONE): "NONE"
-Cache model (NUCA, UCA)  - "UCA"
-NUCA bank count 0
-Wire signalling (fullswing, lowswing, default) - "Global_30"
-Wire inside mat - "semi-global"
-Wire outside mat - "semi-global"
-Interconnect projection - "conservative"
-Core count 1
-Cache level (L2/L3) - "L2"
-Add ECC - "true"
-Print level (DETAILED, CONCISE) - "DETAILED"
-Print input parameters - "true"
-Force cache config - "false"
-Ndwl 1
-Ndbl 1
-Nspd 0
-Ndcm 1
-Ndsam1 0
-Ndsam2 0