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CHANGELOG.rst

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SDRAM library change log

3.2.0

  • Automatic setting of port delays for a given clock divider
  • Fixes to initialization
  • Improved read and write latency
  • Documentaion and API fixes
  • Support for new xCORE-200 Slice Kit in examples

3.1.0

  • Support for 9b row address (128Mb and 256Mb SDRAMs) for xCORE-200 targets
  • Fixes incorrect use of READ/WRITE with auto precharge
  • Updated example and test to support xCORE-200 by default

3.0.2

  • Update to source code license and copyright

3.0.1

  • Added support for xCORE-200 series

3.0.0

  • Consolidated version, major rework from previous SDRAM components