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filmgrain16_sse.asm
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filmgrain16_sse.asm
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; Copyright © 2021, VideoLAN and dav1d authors
; Copyright © 2021, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
%include "config.asm"
%include "ext/x86/x86inc.asm"
%include "x86/filmgrain_common.asm"
SECTION_RODATA 16
pd_16: times 4 dd 16
pw_1: times 8 dw 1
pw_16384: times 8 dw 16384
pw_8192: times 8 dw 8192
pw_23_22: dw 23, 22
times 3 dw 0, 32
pb_mask: db 0, 0x80, 0x80, 0, 0x80, 0, 0, 0x80, 0x80, 0, 0, 0x80, 0, 0x80, 0x80, 0
pw_27_17_17_27: dw 27, 17, 17, 27
times 2 dw 0, 32
rnd_next_upperbit_mask: dw 0x100B, 0x2016, 0x402C, 0x8058
pw_seed_xor: times 2 dw 0xb524
times 2 dw 0x49d8
pb_1: times 4 db 1
hmul_bits: dw 32768, 16384, 8192, 4096
round: dw 2048, 1024, 512
mul_bits: dw 256, 128, 64, 32, 16
round_vals: dw 32, 64, 128, 256, 512, 1024
max: dw 256*4-1, 240*4, 235*4, 256*16-1, 240*16, 235*16
min: dw 0, 16*4, 16*16
; these two should be next to each other
pw_4: times 2 dw 4
pw_16: times 2 dw 16
%macro JMP_TABLE 1-*
%xdefine %1_table %%table
%xdefine %%base %1_table
%xdefine %%prefix mangle(private_prefix %+ _%1)
%%table:
%rep %0 - 1
dd %%prefix %+ .ar%2 - %%base
%rotate 1
%endrep
%endmacro
JMP_TABLE generate_grain_y_16bpc_ssse3, 0, 1, 2, 3
JMP_TABLE generate_grain_uv_420_16bpc_ssse3, 0, 1, 2, 3
JMP_TABLE generate_grain_uv_422_16bpc_ssse3, 0, 1, 2, 3
JMP_TABLE generate_grain_uv_444_16bpc_ssse3, 0, 1, 2, 3
SECTION .text
%if ARCH_X86_32
%undef base
%define PIC_ptr(a) base+a
%else
%define PIC_ptr(a) a
%endif
%define m(x) mangle(private_prefix %+ _ %+ x %+ SUFFIX)
%macro vpgatherdw 5-8 8, 1 ; dst, src, base, tmp_gpr[x2], cnt, stride, tmp_xmm_reg
%assign %%idx 0
%define %%tmp %2
%if %0 == 8
%define %%tmp %8
%endif
%rep (%6/2)
%if %%idx == 0
movd %5 %+ d, %2
pshuflw %%tmp, %2, q3232
%else
movd %5 %+ d, %%tmp
%if %6 == 8
%if %%idx == 2
punpckhqdq %%tmp, %%tmp
%elif %%idx == 4
psrlq %%tmp, 32
%endif
%endif
%endif
movzx %4 %+ d, %5 %+ w
shr %5 %+ d, 16
%if %%idx == 0
movd %1, [%3+%4*%7]
%else
pinsrw %1, [%3+%4*%7], %%idx + 0
%endif
pinsrw %1, [%3+%5*%7], %%idx + 1
%assign %%idx %%idx+2
%endrep
%endmacro
%macro SPLATD 2 ; dst, src
%ifnidn %1, %2
movd %1, %2
%endif
pshufd %1, %1, q0000
%endmacro
%macro SPLATW 2 ; dst, src
%ifnidn %1, %2
movd %1, %2
%endif
pshuflw %1, %1, q0000
punpcklqdq %1, %1
%endmacro
INIT_XMM ssse3
%if ARCH_X86_64
cglobal generate_grain_y_16bpc, 3, 8, 16, buf, fg_data, bdmax
lea r4, [pb_mask]
%define base r4-pb_mask
%else
cglobal generate_grain_y_16bpc, 3, 6, 8, buf, fg_data, bdmax
LEA r4, $$
%define base r4-$$
%endif
movq m1, [base+rnd_next_upperbit_mask]
movq m4, [base+mul_bits]
movq m7, [base+hmul_bits]
mov r3d, [fg_dataq+FGData.grain_scale_shift]
lea r5d, [bdmaxq+1]
shr r5d, 11 ; 0 for 10bpc, 2 for 12bpc
sub r3, r5
SPLATW m6, [base+round+r3*2-2]
mova m5, [base+pb_mask]
SPLATW m0, [fg_dataq+FGData.seed]
mov r3, -73*82*2
sub bufq, r3
%if ARCH_X86_64
lea r6, [gaussian_sequence]
%endif
.loop:
pand m2, m0, m1
psrlw m3, m2, 10
por m2, m3 ; bits 0xf, 0x1e, 0x3c and 0x78 are set
pmullw m2, m4 ; bits 0x0f00 are set
pshufb m3, m5, m2 ; set 15th bit for next 4 seeds
psllq m2, m3, 30
por m2, m3
psllq m3, m2, 15
por m2, m3 ; aggregate each bit into next seed's high bit
pmulhuw m3, m0, m7
por m2, m3 ; 4 next output seeds
pshuflw m0, m2, q3333
psrlw m2, 5
%if ARCH_X86_64
vpgatherdw m3, m2, r6, r5, r7, 4, 2
%else
vpgatherdw m3, m2, base+gaussian_sequence, r5, r2, 4, 2
%endif
paddw m3, m3 ; otherwise bpc=12 w/ grain_scale_shift=0
; shifts by 0, which pmulhrsw does not support
pmulhrsw m3, m6
movq [bufq+r3], m3
add r3, 4*2
jl .loop
; auto-regression code
movsxd r3, [fg_dataq+FGData.ar_coeff_lag]
movsxd r3, [base+generate_grain_y_16bpc_ssse3_table+r3*4]
lea r3, [r3+base+generate_grain_y_16bpc_ssse3_table]
jmp r3
.ar1:
%if WIN64
DEFINE_ARGS shift, fg_data, max, buf, val3, min, cf3, x, val0
lea bufq, [r0-2*(82*73-(82*3+79))]
PUSH r8
%else
%if ARCH_X86_64
DEFINE_ARGS buf, fg_data, max, shift, val3, min, cf3, x, val0
%else ; x86-32
DEFINE_ARGS buf, fg_data, min, val3, x, cf3, val0
PUSH r6
%define shiftd r1d
%endif
sub bufq, 2*(82*73-(82*3+79))
%endif
movsx cf3d, byte [fg_dataq+FGData.ar_coeffs_y+3]
movd m4, [fg_dataq+FGData.ar_coeffs_y]
mov shiftd, [fg_dataq+FGData.ar_coeff_shift]
%if WIN64
DEFINE_ARGS shift, h, max, buf, val3, min, cf3, x, val0
%elif ARCH_X86_64
DEFINE_ARGS buf, h, max, shift, val3, min, cf3, x, val0
%else ; x86-32
%undef shiftd
DEFINE_ARGS buf, shift, min, val3, x, cf3, val0
%define hd dword r0m
%define maxd dword minm
%endif
%if cpuflag(sse4)
pmovsxbw m4, m4
%else
pxor m3, m3
pcmpgtb m3, m4
punpcklbw m4, m3
%endif
pinsrw m4, [base+pw_1], 3
pshufd m5, m4, q1111
pshufd m4, m4, q0000
SPLATW m3, [base+round_vals+shiftq*2-12] ; rnd
mov hd, 70
sar maxd, 1
mov mind, maxd
xor mind, -1
.y_loop_ar1:
mov xq, -76
movsx val3d, word [bufq+xq*2-2]
.x_loop_ar1:
movu m0, [bufq+xq*2-82*2-2] ; top/left
psrldq m2, m0, 2 ; top
psrldq m1, m0, 4 ; top/right
punpcklwd m0, m2
punpcklwd m1, m3
pmaddwd m0, m4
pmaddwd m1, m5
paddd m0, m1
.x_loop_ar1_inner:
movd val0d, m0
psrldq m0, 4
imul val3d, cf3d
add val3d, val0d
sar val3d, shiftb
movsx val0d, word [bufq+xq*2]
add val3d, val0d
cmp val3d, maxd
cmovg val3d, maxd
cmp val3d, mind
cmovl val3d, mind
mov word [bufq+xq*2], val3w
; keep val3d in-place as left for next x iteration
inc xq
jz .x_loop_ar1_end
test xq, 3
jnz .x_loop_ar1_inner
jmp .x_loop_ar1
.x_loop_ar1_end:
add bufq, 82*2
dec hd
jg .y_loop_ar1
%if WIN64
POP r8
%elif ARCH_X86_32
POP r6
%undef maxd
%undef hd
%endif
.ar0:
RET
.ar2:
%if ARCH_X86_32
%assign stack_offset_old stack_offset
ALLOC_STACK -16*8
%endif
DEFINE_ARGS buf, fg_data, bdmax, shift
mov shiftd, [fg_dataq+FGData.ar_coeff_shift]
movd m0, [base+round_vals-12+shiftq*2]
pshuflw m0, m0, q0000
movu m6, [fg_dataq+FGData.ar_coeffs_y+0] ; cf0-11
pxor m2, m2
punpcklwd m0, m2
pcmpgtb m2, m6
punpckhbw m3, m6, m2
punpcklbw m6, m2
pshufd m2, m6, q3333
pshufd m1, m6, q2222
pshufd m7, m6, q1111
pshufd m6, m6, q0000
pshufd m4, m3, q1111
pshufd m3, m3, q0000
%if ARCH_X86_64
SWAP 0, 12
SWAP 1, 8
SWAP 2, 9
SWAP 3, 10
SWAP 4, 11
%else
%define m12 [rsp+0*16]
%define m8 [rsp+1*16]
%define m9 [rsp+2*16]
%define m10 [rsp+3*16]
%define m11 [rsp+4*16]
mova m12, m0
mova m8, m1
mova m9, m2
mova m10, m3
mova m11, m4
mov bdmaxd, bdmaxm
%endif
sar bdmaxd, 1
SPLATW m0, bdmaxd ; max_grain
pcmpeqw m1, m1
%if !cpuflag(sse4)
pcmpeqw m2, m2
psrldq m2, 14
pslldq m2, 2
pxor m2, m1
%endif
pxor m1, m0 ; min_grain
%if ARCH_X86_64
SWAP 0, 13
SWAP 1, 14
SWAP 2, 15
%else
%define m13 [rsp+5*16]
%define m14 [rsp+6*16]
mova m13, m0
mova m14, m1
%if !cpuflag(sse4)
%define m15 [rsp+7*16]
mova m15, m2
%endif
%endif
sub bufq, 2*(82*73-(82*3+79))
DEFINE_ARGS buf, fg_data, h, x
mov hd, 70
.y_loop_ar2:
mov xq, -76
.x_loop_ar2:
movu m0, [bufq+xq*2-82*4-4] ; y=-2,x=[-2,+5]
movu m1, [bufq+xq*2-82*2-4] ; y=-1,x=[-2,+5]
psrldq m2, m0, 2
psrldq m3, m0, 4
psrldq m4, m0, 6
psrldq m5, m0, 8
punpcklwd m0, m2
punpcklwd m3, m4
punpcklwd m5, m1
psrldq m2, m1, 2
psrldq m4, m1, 4
punpcklwd m2, m4
psrldq m4, m1, 6
psrldq m1, 8
punpcklwd m4, m1
pmaddwd m0, m6
pmaddwd m3, m7
pmaddwd m5, m8
pmaddwd m2, m9
pmaddwd m4, m10
paddd m0, m3
paddd m5, m2
paddd m0, m4
paddd m0, m5 ; accumulated top 2 rows
paddd m0, m12
movu m1, [bufq+xq*2-4] ; y=0,x=[-2,+5]
pshufd m4, m1, q3321
pxor m2, m2
pcmpgtw m2, m4
punpcklwd m4, m2 ; in dwords, y=0,x=[0,3]
.x_loop_ar2_inner:
pmaddwd m2, m1, m11
paddd m2, m0
psrldq m0, 4 ; shift top to next pixel
psrad m2, [fg_dataq+FGData.ar_coeff_shift]
paddd m2, m4
packssdw m2, m2
pminsw m2, m13
pmaxsw m2, m14
psrldq m4, 4
pslldq m2, 2
psrldq m1, 2
%if cpuflag(sse4)
pblendw m1, m2, 00000010b
%else
pand m1, m15
pandn m3, m15, m2
por m1, m3
%endif
; overwrite previous pixel, this should be ok
movd [bufq+xq*2-2], m1
inc xq
jz .x_loop_ar2_end
test xq, 3
jnz .x_loop_ar2_inner
jmp .x_loop_ar2
.x_loop_ar2_end:
add bufq, 82*2
dec hd
jg .y_loop_ar2
%if ARCH_X86_32
%undef m8
%undef m9
%undef m10
%undef m11
%undef m12
%undef m13
%undef m14
%undef m15
%endif
RET
.ar3:
DEFINE_ARGS buf, fg_data, bdmax, shift
%if WIN64
mov r6, rsp
and rsp, ~15
sub rsp, 64
%define tmp rsp
%elif ARCH_X86_64
%define tmp rsp+stack_offset-72
%else
%assign stack_offset stack_offset_old
ALLOC_STACK -16*12
%define tmp rsp
mov bdmaxd, bdmaxm
%endif
sar bdmaxd, 1
SPLATW m7, bdmaxd ; max_grain
pcmpeqw m6, m6
%if !cpuflag(sse4)
pcmpeqw m4, m4
psrldq m4, 14
pslldq m4, 4
pxor m4, m6
%endif
pxor m6, m7 ; min_grain
mov shiftd, [fg_dataq+FGData.ar_coeff_shift]
%if ARCH_X86_64
SWAP 6, 14
SWAP 7, 15
%else
%define m14 [rsp+10*16]
%define m15 [esp+11*16]
mova m14, m6
mova m15, m7
%endif
; build cf0-1 until 18-19 in m5-12 and r0/1
pxor m1, m1
movu m0, [fg_dataq+FGData.ar_coeffs_y+ 0] ; cf0-15
pcmpgtb m1, m0
punpckhbw m2, m0, m1
punpcklbw m0, m1
%if cpuflag(sse4)
pshufd m4, m2, q3333
%else
pshufd m5, m2, q3333
mova [tmp+48], m5
%endif
pshufd m3, m2, q2222
pshufd m1, m2, q0000
pshufd m2, m2, q1111
pshufd m7, m0, q2222
pshufd m6, m0, q1111
pshufd m5, m0, q0000
pshufd m0, m0, q3333
%if ARCH_X86_64
SWAP 0, 8
SWAP 1, 9
SWAP 2, 10
SWAP 3, 11
SWAP 4, 12
%else
%define m8 [rsp+4*16]
%define m9 [esp+5*16]
%define m10 [rsp+6*16]
%define m11 [esp+7*16]
%define m12 [rsp+8*16]
mova m8, m0
mova m9, m1
mova m10, m2
mova m11, m3
mova m12, m4
%endif
; build cf20,round in r2
; build cf21-23,round*2 in m13
pxor m1, m1
movq m0, [fg_dataq+FGData.ar_coeffs_y+16] ; cf16-23
pcmpgtb m1, m0
punpcklbw m0, m1
pshufd m1, m0, q0000
pshufd m2, m0, q1111
mova [tmp+ 0], m1
mova [tmp+16], m2
psrldq m3, m0, 10
pinsrw m3, [base+round_vals+shiftq*2-10], 3
%if ARCH_X86_64
SWAP 3, 13
%else
%define m13 [esp+9*16]
mova m13, m3
%endif
pinsrw m0, [base+round_vals+shiftq*2-12], 5
pshufd m3, m0, q2222
mova [tmp+32], m3
DEFINE_ARGS buf, fg_data, h, x
sub bufq, 2*(82*73-(82*3+79))
mov hd, 70
.y_loop_ar3:
mov xq, -76
.x_loop_ar3:
movu m0, [bufq+xq*2-82*6-6+ 0] ; y=-3,x=[-3,+4]
movd m1, [bufq+xq*2-82*6-6+16] ; y=-3,x=[+5,+6]
palignr m2, m1, m0, 2 ; y=-3,x=[-2,+5]
palignr m1, m1, m0, 12 ; y=-3,x=[+3,+6]
punpckhwd m3, m0, m2 ; y=-3,x=[+1/+2,+2/+3,+3/+4,+4/+5]
punpcklwd m0, m2 ; y=-3,x=[-3/-2,-2/-1,-1/+0,+0/+1]
shufps m2, m0, m3, q1032 ; y=-3,x=[-1/+0,+0/+1,+1/+2,+2/+3]
pmaddwd m0, m5
pmaddwd m2, m6
pmaddwd m3, m7
paddd m0, m2
paddd m0, m3
; m0 = top line first 6 multiplied by cf, m1 = top line last entry
movu m2, [bufq+xq*2-82*4-6+ 0] ; y=-2,x=[-3,+4]
movd m3, [bufq+xq*2-82*4-6+16] ; y=-2,x=[+5,+6]
punpcklwd m1, m2 ; y=-3/-2,x=[+3/-3,+4/-2,+5/-1,+6/+0]
palignr m4, m3, m2, 2 ; y=-3,x=[-2,+5]
palignr m3, m3, m2, 4 ; y=-3,x=[-1,+6]
punpckhwd m2, m4, m3 ; y=-2,x=[+2/+3,+3/+4,+4/+5,+5/+6]
punpcklwd m4, m3 ; y=-2,x=[-2/-1,-1/+0,+0/+1,+1/+2]
shufps m3, m4, m2, q1032 ; y=-2,x=[+0/+1,+1/+2,+2/+3,+3/+4]
pmaddwd m1, m8
pmaddwd m4, m9
pmaddwd m3, m10
pmaddwd m2, m11
paddd m1, m4
paddd m3, m2
paddd m0, m1
paddd m0, m3
; m0 = top 2 lines multiplied by cf
movu m1, [bufq+xq*2-82*2-6+ 0] ; y=-1,x=[-3,+4]
movd m2, [bufq+xq*2-82*2-6+16] ; y=-1,x=[+5,+6]
palignr m3, m2, m1, 2 ; y=-1,x=[-2,+5]
palignr m2, m2, m1, 12 ; y=-1,x=[+3,+6]
punpckhwd m4, m1, m3 ; y=-1,x=[+1/+2,+2/+3,+3/+4,+4/+5]
punpcklwd m1, m3 ; y=-1,x=[-3/-2,-2/-1,-1/+0,+0/+1]
shufps m3, m1, m4, q1032 ; y=-1,x=[-1/+0,+0/+1,+1/+2,+2/+3]
punpcklwd m2, [base+pw_1]
%if cpuflag(sse4)
pmaddwd m1, m12
%else
pmaddwd m1, [tmp+48]
%endif
pmaddwd m3, [tmp+ 0]
pmaddwd m4, [tmp+16]
pmaddwd m2, [tmp+32]
paddd m1, m3
paddd m4, m2
paddd m0, m1
paddd m0, m4
; m0 = top 3 lines multiplied by cf plus rounding for downshift
movu m1, [bufq+xq*2-6] ; y=0,x=[-3,+4]
.x_loop_ar3_inner:
pmaddwd m2, m1, m13
pshufd m3, m2, q1111
paddd m2, m3 ; left+cur
paddd m2, m0 ; add top
psrldq m0, 4
psrad m2, [fg_dataq+FGData.ar_coeff_shift]
packssdw m2, m2
pminsw m2, m15
pmaxsw m2, m14
pslldq m2, 4
psrldq m1, 2
%if cpuflag(sse4)
pblendw m1, m2, 00000100b
%else
pand m1, m12
pandn m3, m12, m2
por m1, m3
%endif
; overwrite a couple of pixels, should be ok
movq [bufq+xq*2-4], m1
inc xq
jz .x_loop_ar3_end
test xq, 3
jnz .x_loop_ar3_inner
jmp .x_loop_ar3
.x_loop_ar3_end:
add bufq, 82*2
dec hd
jg .y_loop_ar3
%if WIN64
mov rsp, r6
%elif ARCH_X86_32
%undef m8
%undef m9
%undef m10
%undef m11
%undef m12
%undef m13
%undef m14
%undef m15
%endif
RET
%macro generate_grain_uv_fn 3 ; ss_name, ss_x, ss_y
INIT_XMM ssse3
%if ARCH_X86_64
cglobal generate_grain_uv_%1_16bpc, 4, 11, 16, buf, bufy, fg_data, uv, bdmax, x, gaussian_reg, h, pic_reg
%define base r8-pb_mask
lea r8, [pb_mask]
movifnidn bdmaxd, bdmaxm
lea r6d, [bdmaxq+1]
%else
cglobal generate_grain_uv_%1_16bpc, 1, 7, 8, buf, x, pic_reg, fg_data, h
%define base r2-$$
LEA r2, $$
mov fg_dataq, r2m
mov r6d, r4m
inc r6d
%endif
movq m1, [base+rnd_next_upperbit_mask]
movq m4, [base+mul_bits]
movq m7, [base+hmul_bits]
mov r5d, [fg_dataq+FGData.grain_scale_shift]
shr r6d, 11 ; 0 for 10bpc, 2 for 12bpc
sub r5, r6
SPLATW m6, [base+round+r5*2-2]
mova m5, [base+pb_mask]
SPLATW m0, [fg_dataq+FGData.seed]
%if ARCH_X86_64
SPLATW m2, [base+pw_seed_xor+uvq*4]
%else
mov r5d, r3m
SPLATW m2, [base+pw_seed_xor+r5*4]
%endif
pxor m0, m2
%if ARCH_X86_64
lea r6, [gaussian_sequence]
%endif
%if %2
mov hd, 73-35*%3
add bufq, 44*2
.loop_y:
mov xq, -44
%else
mov xq, -82*73
add bufq, 82*73*2
%endif
.loop_x:
pand m2, m0, m1
psrlw m3, m2, 10
por m2, m3 ; bits 0xf, 0x1e, 0x3c and 0x78 are set
pmullw m2, m4 ; bits 0x0f00 are set
pshufb m3, m5, m2 ; set 15th bit for next 4 seeds
psllq m2, m3, 30
por m2, m3
psllq m3, m2, 15
por m2, m3 ; aggregate each bit into next seed's high bit
pmulhuw m3, m0, m7
por m2, m3 ; 4 next output seeds
pshuflw m0, m2, q3333
psrlw m2, 5
%if ARCH_X86_64
vpgatherdw m3, m2, r6, r9, r10, 4, 2
%else
vpgatherdw m3, m2, base+gaussian_sequence, r5, r6, 4, 2
%endif
paddw m3, m3 ; otherwise bpc=12 w/ grain_scale_shift=0
; shifts by 0, which pmulhrsw does not support
pmulhrsw m3, m6
movq [bufq+xq*2], m3
add xq, 4
jl .loop_x
%if %2
add bufq, 82*2
dec hd
jg .loop_y
%endif
; auto-regression code
movsxd r5, [fg_dataq+FGData.ar_coeff_lag]
movsxd r5, [base+generate_grain_uv_%1_16bpc_ssse3_table+r5*4]
lea r5, [r5+base+generate_grain_uv_%1_16bpc_ssse3_table]
jmp r5
.ar0:
%if ARCH_X86_64
DEFINE_ARGS buf, bufy, fg_data, uv, bdmax, shift
%else
DEFINE_ARGS buf, bufy, pic_reg, fg_data, uv, shift
%assign stack_offset_old stack_offset
ALLOC_STACK -16*2
mov bufyq, r1m
mov uvd, r3m
%endif
imul uvd, 28
mov shiftd, [fg_dataq+FGData.ar_coeff_shift]
movd m4, [fg_dataq+FGData.ar_coeffs_uv+uvq]
SPLATW m3, [base+hmul_bits+shiftq*2-10]
%if ARCH_X86_64
sar bdmaxd, 1
SPLATW m1, bdmaxd ; max_gain
%else
SPLATW m1, r4m
psraw m1, 1
%endif
pcmpeqw m7, m7
pxor m7, m1 ; min_grain
%if ARCH_X86_64
SWAP 1, 14
DEFINE_ARGS buf, bufy, h, x
%else
%define m14 [rsp+0*16]
mova m14, m1
DEFINE_ARGS buf, bufy, pic_reg, h, x
%endif
pxor m5, m5
pcmpgtb m5, m4
punpcklbw m4, m5
%if %2
SPLATW m6, [base+hmul_bits+2+%3*2]
%endif
SPLATW m4, m4
pxor m5, m5
%if %2
%if !cpuflag(sse4)
pcmpeqw m2, m2
pslldq m2, 12
%if ARCH_X86_64
SWAP 2, 12
%else
%define m12 [rsp+1*16]
mova m12, m2
%endif
%endif
%endif
%if %2
sub bufq, 2*(82*(73-35*%3)+82-(82*3+41))
%else
sub bufq, 2*(82*70-3)
%endif
add bufyq, 2*(3+82*3)
mov hd, 70-35*%3
.y_loop_ar0:
; first 32 pixels
xor xd, xd
.x_loop_ar0:
movu m0, [bufyq+xq*(2<<%2)]
%if %2
%if %3
movu m2, [bufyq+xq*4+82*2]
paddw m0, m2
%endif
movu m1, [bufyq+xq*4 +16]
%if %3
movu m2, [bufyq+xq*4+82*2+16]
paddw m1, m2
%endif
phaddw m0, m1
pmulhrsw m0, m6
%endif
punpckhwd m1, m0, m5
punpcklwd m0, m5
REPX {pmaddwd x, m4}, m0, m1
REPX {psrad x, 5}, m0, m1
packssdw m0, m1
pmulhrsw m0, m3
movu m1, [bufq+xq*2]
paddw m0, m1
pminsw m0, m14
pmaxsw m0, m7
cmp xd, 72-40*%2
je .end
movu [bufq+xq*2], m0
add xd, 8
jmp .x_loop_ar0
; last 6/4 pixels
.end:
%if %2
%if cpuflag(sse4)
pblendw m0, m1, 11000000b
%else
pand m1, m12
pandn m2, m12, m0
por m0, m1, m2
%endif
movu [bufq+xq*2], m0
%else
movq [bufq+xq*2], m0
%endif
add bufq, 82*2
add bufyq, 82*(2<<%3)
dec hd
jg .y_loop_ar0
%if ARCH_X86_32
%undef m12
%undef m14
%endif
RET
.ar1:
%if ARCH_X86_64
DEFINE_ARGS buf, bufy, fg_data, uv, max, cf3, min, val3, x
%else
%assign stack_offset stack_offset_old
%xdefine rstk rsp
%assign stack_size_padded 0
DEFINE_ARGS buf, shift, pic_reg, fg_data, uv, bufy, cf3
mov bufyq, r1m
mov uvd, r3m
%endif
imul uvd, 28
movsx cf3d, byte [fg_dataq+FGData.ar_coeffs_uv+uvq+3]
movq m4, [fg_dataq+FGData.ar_coeffs_uv+uvq]
%if WIN64
DEFINE_ARGS shift, bufy, h, buf, max, cf3, min, val3, x, val0
%if %2
lea bufq, [r0-2*(82*(73-35*%3)+44-(82*3+41))]
%else
lea bufq, [r0-2*(82*69+3)]
%endif
%else
%if ARCH_X86_64
DEFINE_ARGS buf, bufy, h, shift, max, cf3, min, val3, x, val0
%else
DEFINE_ARGS buf, shift, pic_reg, fg_data, val0, bufy, cf3
%define hd dword r1m
%define mind dword r3m
%define maxd dword r4m
%endif
%if %2
sub bufq, 2*(82*(73-35*%3)+44-(82*3+41))
%else
sub bufq, 2*(82*69+3)
%endif
%endif
%if ARCH_X86_64
mov shiftd, [r2+FGData.ar_coeff_shift]
%else
mov shiftd, [r3+FGData.ar_coeff_shift]
%endif
pxor m5, m5
pcmpgtb m5, m4
punpcklbw m4, m5 ; cf0-4 in words
pshuflw m4, m4, q2100
psrldq m4, 2 ; cf0-3,4 in words
pshufd m5, m4, q1111
pshufd m4, m4, q0000
movd m3, [base+round_vals+shiftq*2-12] ; rnd
pxor m6, m6
punpcklwd m3, m6
%if %2
SPLATW m6, [base+hmul_bits+2+%3*2]
%endif
SPLATD m3, m3
add bufyq, 2*(79+82*3)
mov hd, 70-35*%3
sar maxd, 1
%if ARCH_X86_64
mov mind, maxd
xor mind, -1
%else
DEFINE_ARGS buf, shift, val3, x, val0, bufy, cf3
mov r2, maxd
xor r2, -1
mov mind, r2
%endif
.y_loop_ar1:
mov xq, -(76>>%2)
movsx val3d, word [bufq+xq*2-2]
.x_loop_ar1:
movu m0, [bufq+xq*2-82*2-2] ; top/left
%if %2
movu m7, [bufyq+xq*4]
%if %3
movu m1, [bufyq+xq*4+82*2]
phaddw m7, m1
%else
phaddw m7, m7
%endif
%else
movq m7, [bufyq+xq*2]
%endif
psrldq m2, m0, 2 ; top
psrldq m1, m0, 4 ; top/right
punpcklwd m0, m2
%if %2
%if %3
pshufd m2, m7, q3232
paddw m7, m2
%endif
pmulhrsw m7, m6
%endif
punpcklwd m1, m7
pmaddwd m0, m4
pmaddwd m1, m5
paddd m0, m1
paddd m0, m3
.x_loop_ar1_inner:
movd val0d, m0
psrldq m0, 4
imul val3d, cf3d
add val3d, val0d
sar val3d, shiftb
movsx val0d, word [bufq+xq*2]
add val3d, val0d
cmp val3d, maxd
cmovg val3d, maxd
cmp val3d, mind
cmovl val3d, mind
mov word [bufq+xq*2], val3w
; keep val3d in-place as left for next x iteration
inc xq
jz .x_loop_ar1_end
test xq, 3
jnz .x_loop_ar1_inner
jmp .x_loop_ar1
.x_loop_ar1_end:
add bufq, 82*2
add bufyq, 82*2<<%3
dec hd
jg .y_loop_ar1
%if ARCH_X86_32
%undef maxd
%undef mind
%undef hd
%endif
RET
.ar2:
%if ARCH_X86_64
DEFINE_ARGS buf, bufy, fg_data, uv, bdmax, shift
%else
DEFINE_ARGS buf, bufy, pic_reg, fg_data, uv, shift
ALLOC_STACK -16*8
mov bufyq, r1m
mov uvd, r3m
%endif
mov shiftd, [fg_dataq+FGData.ar_coeff_shift]
imul uvd, 28
%if ARCH_X86_64
sar bdmaxd, 1
SPLATW m5, bdmaxd ; max_grain
%else
SPLATW m5, r4m
psraw m5, 1
%endif
pcmpeqw m6, m6
%if !cpuflag(sse4)
pcmpeqw m7, m7
psrldq m7, 14
pslldq m7, 2
pxor m7, m6
%endif
pxor m6, m5 ; min_grain
%if %2 && cpuflag(sse4)
SPLATW m7, [base+hmul_bits+2+%3*2]
%endif
%if ARCH_X86_64
SWAP 5, 13
SWAP 6, 14
SWAP 7, 15
%else
%define m13 [rsp+5*16]
%define m14 [rsp+6*16]
%define m15 [rsp+7*16]
mova m13, m5
mova m14, m6
mova m15, m7